Panasonic Corporation

Socionext Inc.

Yoshinobu Yamagami

Satoshi Ishikura

Marefusa Kurumada

Toshio Terano

Toshikazu Suzuki

Yasuhiro Agata

Tsuyoshi Koike

Hiroaki Okuyama

Hironori Akamatsu

Kazuo Itoh

Makoto Kojima

Yutaka Terada

Masanori Shirahama

Naoki Kuroda

Masanobu Hirose

Katsuji Satomi

Shinichi Moriwaki

Akira Masuo

Hiroyuki Yamauchi

Noriaki Narumi

Hideo Akiyoshi

Tomoyuki Aihara

Masataka Sato

A semiconductor storage device including a two-port SRAM cell, in which nanosheetstoare formed in line in this order in the X direction, and nanosheetstoare formed in line in this order in the X direction. Faces of the nanosheets, andon the first side in the X direction are exposed from gate interconnects, and, respectively. Faces of the nanosheets, andon the second side in the X direction are exposed from gate interconnects, and, respectively.

Two port SRAM device using forked nanosheet FETs

Static Random Access Memory (SRAM) cell using Complementary FET (CFET) includes the first to sixth transistors each of which is a three-dimensional transistor. The first to fourth transistors are formed at the same position as each other in the first direction in which channel portions of the first to sixth transistors extend. The fifth transistor having a node connected to the first bit line and the sixth transistor having a node connected to the second bit line are formed at the same position in the first direction as each other.

Semiconductor storage device

Provided is a layout structure capable of reducing the parasitic capacitance between storage nodes of an SRAM cell using vertical nanowire (VNW) FETs. In the SRAM cell, a first storage node is connected to top electrodes of some transistors, and a second storage node is connected to bottom electrodes of other transistors. Accordingly, the first and second storage nodes have fewer regions adjacent to each other in a single layer.

Semiconductor integrated circuit device

A memory cell of a 2-port static random access memory (SRAM) includes first and second p-type transistors and first to sixth n-type transistors. Gate interconnects extend in the X direction and are arranged in three rows in the Y direction. The gate interconnects in the first row form gates of the first n-type transistor, the first p-type transistor, and the fourth n-type transistor, the gate interconnect in the second row forms gates of the fifth and sixth n-type transistors, and the gate interconnects in the third row form gates of the third n-type transistor, the second n-type transistor, and the second p-type transistor.

Semiconductor memory device

First and second memory cell arrays each having memory cells arranged in the X and Y directions lie side by side in the Y direction with space between them. A relay buffer is provided between first and second row decoders for buffering a control signal to be supplied to the second row decoder. An inter-array block between the first and second memory cell arrays is constituted by at least either a tap cell or a dummy memory cell. The relay buffer and the inter-array block are the same in position and size in the Y direction.

Semiconductor storage circuit

A semiconductor storage circuit has: a plurality of first memory cells and a first precharge transistor connected to a first local read bit line; and a plurality of second memory cells and a second precharge transistor connected to a second local read bit line. A signal responsive to signals output to the first and second local read bit lines is output to a global read bit line via a gate circuit and an output circuit. A first transistor having a gate connected to the output of the gate circuit is provided between the first and second local read bit lines.

Semiconductor storage circuit, semiconductor storage apparatus, and data detection method

In a semiconductor memory device, a memory cell array includes a plurality of memory cells. A write circuit includes a negative potential generating circuit that generates a potential lower than a lower power supply potential applied to the memory cells. When a write mask signal indicates an enabled state, the write circuit activates the negative potential generating circuit, and supplies the potential generated by the negative potential generating circuit to a bit line to be supplied with low data. On the other hand, when the write mask signal indicates a disabled state, the write circuit supplies no data to bit line pairs, and inactivates the negative potential generating circuit.

Semiconductor memory device and data writing method

Disclosed herein is a driver circuit including a first group of transistors provided between first and second nodes and including n of the transistor(s) where n is equal to or greater than one, and a second group of transistors provided in parallel with the first group of transistors and including m of the transistor(s) where m is equal to or greater than one and not equal to n, the m transistors being connected together in series. The n-channel transistor in the first group and at least one of the two n-channel transistors in the second group have their gate connected to an input node.

FINFET based driver circuit

Finfet based driver circuit

A cross-coupled circuit provided between first and second bit lines that form a bit line pair includes first to fourth fin transistors of p-channel type. The first transistor has its source connected to a first power supply and its gate connected to the second bit line. The second transistor has its source connected to the first power supply and its gate connected to the first bit line. The third transistor has its source connected to the first transistor's drain and its drain connected to the first bit line. The fourth transistor has its source connected to the second transistor's drain and its drain connected to the second bit line.

Semiconductor storage device and sense amplifier circuit

A memory cell power supply circuit for each column includes a first PMOS transistor and a second PMOS transistor connected together in series between a first power supply and a second power supply. A connection point between the first and second PMOS transistors is output as a memory cell power supply. A control signal which is based on a column select signal and a write control signal is input to a gate terminal of the first PMOS transistor. A signal which is an inverted version of the signal input to the gate terminal of the first PMOS transistor is input to a gate terminal of the second PMOS transistor.

A semiconductor memory device includes a memory cell connected to a word line and a bit line, for storing and holding data, a word line driver circuit connected to the word line, a bit line precharge circuit connected to the bit line, and a peripheral control circuit. First power supply VDD is connected to the memory cell and the peripheral control circuit, and first power supply VDD is connected to word line driver circuit and bit line precharge circuit through switching element controlled by first control signal PD.

A semiconductor integrated circuit includes a P-type MOS transistor and two or more N-type MOS transistors connected together in series between a first and a second power supply, an input terminal connected to a gate terminal of the P-type MOS transistor and gate terminals of the two or more N-type MOS transistors, an output terminal which is a connection node between the P-type MOS transistor and one of the two or more N-type MOS transistors connected to the P-type MOS transistor, and one or more capacitors connected to the output terminal. The drive capability of the P-type MOS transistor is higher than the overall drive capability of the two or more N-type MOS transistors connected together in series. Therefore, a semiconductor integrated circuit is provided in which fluctuations in the delay time of a delay circuit caused by variations in transistor characteristics can be reduced.

Semiconductor integrated circuit

A system LSI () having a logic circuit () and a plurality of SRAM macros () includes a power supply circuit () configured to receive a voltage (VDDP) supplied from the outside of the system LSI (), and to generate a stabilized voltage (VDDM) lower than the voltage (VDDP). An SRAM memory cell () of each of the plurality of SRAM macros () is supplied with the voltage (VDDM) generated by the power supply circuit (), and an SRAM logic circuit () of each of the plurality of SRAM macros () is supplied with a voltage (VDD) supplied from the outside. In addition, the logic circuit () is supplied with the voltage (VDD) from the outside.

A semiconductor memory device includes a first inverter and a second inverter each having an input and an output, the output of each of the first and second inverters being connected to the input of the other so that data is stored, a CMOS switch configured to connect the input of the first inverter and a write bit line, a read MOS transistor having a gate connected to the output of the first inverter, and a MOS switch configured to connect the read MOS transistor to a read bit line. The first and second inverters have different sizes and are connected to different source power supplies.

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Osaka, Japan

Yoshinobu Yamagami