Nec Corporation

Thine Electronics, Inc.

Yoshinobu Oshima

Shunichi Kubo

Yusuke Fujita

Satoru Yamano

Masaki Mitarai

A semiconductor device includes a first circuitand a second circuitthat are connected in series, a first terminal Tthat applies a first potential to a first power supply line DLof the first circuit, a second terminal Tthat applies a second potential to a second power supply line DLof the second circuit, a third terminal Tthat is connected to a signal transfer line of the first circuit, and a protection circuit that is connected to the third terminal T, and discharges a current from the third terminal Tto a fourth terminal Twhen a potential of the third terminal Tbecomes higher than a first threshold value. The first power supply line DLand the second power supply line DLare separated, and the fourth terminal Tis not directly connected to the first power supply line DLand is electrically connected to a lead.

Semiconductor device

A serializer device () includes a first latch unit (), a second latch unit (), a conversion unit (), a frequency division unit (), a load signal generation unit (), a phase difference detection unit (), and a reset instruction unit (), and has a simple configuration and can reduce a bit error rate at an early stage. The phase difference detection unit () detects a phase difference between a first clock (CLK) applied to the first latch unit () and a third clock (CLK) applied to the second latch unit (). The reset instruction unit () outputs a reset instruction signal (RSTn) to the frequency division unit () when the phase difference is not within a target range.

Serializer device

A communication data processing circuit is provided that suitably controls an on/off operation of clock signals, thus effectively reducing the power consumption. The communication data processing circuit processes communication data based on a clock signal to be input. The communication data processing circuit includes a packet processing sectionfor processing communication data, a packet counterfor discriminating between the presence and absence of communication data under process in the packet processing section, and a clock controllerfor inputting or halting a clock signal to the packet processing sectionin response to an output of the packet counter

Communication data processing circuit

A gateway device includes PDTN line terminating portion, audio data processing portion, header processing portion, packet network line terminating portionand gateway control processor. Header processing portionreceives an RTP packet with session number from audio data processing portionand outputs an IP packet attached with UDP/IP header information to packet network line terminating portion. Header processing portionreceives an IP packet from packet network line terminating portionand checks UDP/IP header thereof When the IP packet is an audio packet, header processing portiondeletes the UDP/IP header, attaches a session number thereto and outputs an RTP packet with session number to audio data processing portionand, when the IP packet is an audio packet, header processing portiontransfers it directly to audio data processing portionto send the audio data to the PSTN through PSTN line terminating portion

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Tokyo, Japan

Yoshinobu Oshima