Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Hitachi Denshi Kabushiki Kaisha

Hitachi Vlsi Engineering Corp.

Hitachi Maxell, Limited

Hitachi Device Engineering Co., Ltd.

Hitachi, Vlsi Eng. Corp.

Vlsi Engineering Corporation

Yoshimune Hagiwara

Hideo Nakamura

Kenji Kaneko

Terumi Sawase

Hirotada Ueda

Yuzo Kita

Kouki Noguchi

Tetsuya Nakagawa

Shiro Baba

Hitoshi Matsushima

Yasushi Akao

Takashi Akazawa

Masahito Kobayashi

Atsushi Kiuchi

Narimichi Maeda

Shizuo Sugiyama

Jun Ishida

Katsuaki Takagi

Yasuhiro Kita

Osamu Yumoto

Haruo Koizumi

Tomoru Sato

Tadahiko Nishimukai

Hirokazu Aoki

Atsushi Takai

Shigeki Masumura

Noboru Yamaguchi

Kazuyoshi Ogawa

Kunio Uchiyama

Kiyoshi Matsubara

Katsuhiro Shimohigashi

Yoshio Sakai

Toshiaki Masuhara

Osamu Minato

Yoshiaki Kamigaki

Hideo Sunami

Toru Baji

Shinya Ohba

Shigeru Shimada

Hiroo Masuda

Toshimasa Kihara

Norio Nakagawa

Eiji Takeda

Takaaki Hagiwara

Takashi Tsukamoto

Kazuhiko Iwasaki

Kazuyuki Kodama

Shirou Baba

Fumio Tsuchiya

Hideo Hara

Hirotsugu Kojima

Shuichi Torii

Tadashi Yamaura

Hiroyuki Masuda

You Takamori

Kenji Keneko

Nario Sumi

Noriyasu Suzuki

Tsukasa Sato

Shigehiro Kamejima

Minoru Ishii

Atsuchi Kiuchi

Takanori Toyomasu

Hiroyuki Hatori

Akira Honda

A semiconductor integrated circuit device formed on a single chip or a microcomputer integrated on a semiconductor chip includes a central processing unit (CPU), an interface circuit (or an input/output port), a bus coupled to the CPU and the interface circuit (or the input/output port) and a variable logic circuit (or a subprocessor). The variable logic circuit (or the subprocessor) includes non-volatile memory elements storing instructions, a control circuit generating control signals in accordance with the stored instructions, and an arithmetic logic unit controlled by the generated control signals. Information can be written into the non-volatile memory elements from outside to construct the variable logic circuit or the subprocessor with any desired logical functions. The wiring operation of the memory elements can be executed in a short time, and a user can thus quickly obtain a single-chip microprocessor or a single-chip semiconductor integrated circuit device having hardware of peculiar prescribed specifications.

Single-chip semiconductor integrated circuit device and microcomputer

In developing the function of a data processing system using a semiconductor integrated circuit for data processing, comprising a non-volatile logical function block to which data is written electrically and a logical operation block utilizing the logical function block to execute the logic operation, data corresponding to the required specification and function of the system is written in the logical function block. Thereby, flexibility is obtained for setting and changing the required function to the semiconductor integrated circuit. The semiconductor integrated circuit also has an operation specification written to the logical block by a writing device designed to write to a non-volatile semiconductor storage device thereby improving the convenience of setting the functions required of the semiconductor integrated circuit.

Method for flexibly developing a data processing system comprising

A multi-processor system for multidimensional image signal processing includes a plurality of co-processors and a host processor which issues processor numbers and a command to the co-processors through a bus. Due to the multi-dimensional nature of the processor numbers, data processing for given ranges of an image signal can be shared by the co-processors. A particular multi-dimensional processor number issued by the host computer which allows simultaneous communication to be performed between the host processor and the co-processors.

Multi-processor system and co-processor used for the same

A logic circuit built in a single-chip microprocessor is configured of electrically-programmable memory elements, and information is written into the memory elements from outside, whereby the logic circuit having any desired logical functions can be constructed. The writing operation of the memory elements can be executed in a short time, and a user can obtain the single-chip microprocessor having hardware of peculiar prescribed specifications, in a short period.

Single-chip microcomputer

A typical single chip microcomputer disclosed in the present application comprises a control circuit, a processing circuit and a plurality of address register--status register pairs. A logical unit formed within the control circuit comprises an electrically writable non-volatile-semiconductor memory device. Information can be externally written into the non-volatile semiconductor memory included in the logical unit, and the above described plurality of address register--status register pairs can be arbitrarily selected. As a result, logic function of the logical unit can be arbitrarily established in accordance with externally supplied information. Demanded specifications of various users can be satisfied by the logic function thus arbitrarily formed.

Single chip microprocessor for satisfying requirement specification of

Single-chip microcomputer including non-volatile memory elements

Easy testability and data security of an electrically erasable programmable read only memory (EEPROM) can be accomplished by disposing pads and an input/output (I/O) circuit providing addresses, data and control signals necessary for the EEPROM test on a semiconductor substrate and by disposing a two-level test I/O interception circuit consisting of an EEPROM device on the substrate such that once the testing is completed, unauthorized accessing is prevented from outside the semiconductor substrate as a result of having a built-in data security function. A microcomputer having this capability is provided with a central processing unit (CPU) for processing data, a memory, such as an EEPROM, which is internally communicating through a common bus (which transmits data, address and control signals) with the CPU, other than during a test mode, and first and second inhibition circuits which provide the security. The first inhibition circuit is coupled to the data bus and provides a first inhibition operation to prevent access operations to the memory. The first inhibition circuit release the first inhibiting operation in accordance with a signal from outside the semiconductor substrate or body. The second inhibition means is coupled to the data bus and provides a second inhibiting operation to prevent access operations to the memory from outside the semiconductor body via the data bus and permanently disables the access operations to the memory irrespective of a releasing or termination of the first inhibiting operation after the second inhibiting operation has taken effect.

Microcomputer having a PROM including data security and test circuitry

A microprocessor chip including a ROM portion for storing a microprogram, an execution unit portion for executing an arithmetic operation and random logic circuits disposed between the ROM portion and the execution unit portion. Two-level metal lines technology is used for supplying power for grounding and for providing input/output interconnect lines for the random logic circuits.

Microprocessor chip using two-level metal lines technology

In a microprocessor, a minimum instruction code length is set to a predetermined number of bits (e.g. one byte) length. One feature of the invention is that an instruction set which can selectively expand the instruction code length at a unit of the predetermined number of bits is used. Another feature is that an operand addressing mode and a type of operation for an operand are designated by separate predetermined number of code bits which are coded in a common coding scheme so that an instruction decoder is shared by those codes.

Microprogram controlled microprocessor having a selectively expandable

A microprocessor suitable for a high speed processor system prevents extension of a bus cycle due to delay of generation of a bus cycle end signal and effectively utilizes a characteristic of a high speed accessable external device.

Microprocessor which terminates bus cycle when access address falls

A method of diagnosis of an integrated logic circuit having function blocks, in which a test signal is supplied to the logic circuit; an input signal to and an output signal from at least one of the function blocks are detected by the use of a contactless probing device such as an electron beam probing device or laser beam probing device; simulation is carried out of a normal logic operation of the function block with the detected input signal to provide a simulated output signal; the detected and simulated output signals are compared with each other; and the function block is determined as being normal or abnormal according to the result of the comparison. When the function block includes plural logic elements, the cause of the abnormality may be traced back to a faulty function element by detecting the output of a function element by a contactless probing device, comparing the detected output with a corresponding simulated output and repeating the detection and comparison on other function elements in the function block until the comparison results in coincidence. The function element which receives the signal providing the coincidence as a result of the comparison is determined as the faulty function element.

Method of diagnosing integrated logic circuit

A digital signal processor for determining the maximum and minimum values of a plurality of data items wherein operations of an arithmetic logic unit and data memories are controlled by micro-instructions, including a device for decoding specified bits of an operand of the micro-instruction, a device for detecting a value of a condition code which has been designated by an output of the decoding device, and a control device for executing a logical operation between the output of the detection device, which becomes '1' if the value of the condition code is true, and a decoded value of an operation code of the micro-instruction and to generate a control signal for the arithmetic logic unit on the basis of a result of the logical operation.

Digital signal processor suitable for extacting minimum and maximum

In a single chip processor which can be provided with an extended program memory, a high-speed access can be executed without being restricted by the access time for the external program memory when an internal program memory is employed, by varying the effective instruction cycle, and thus a high-speed processing performance for a single chip processor of a stored program type can be attained.

Single chip processor

A digital signal processor for computing a vector product between a column vector input signal including a plurality of data items (x0, x1, x2, . . . , x7) and a matrix including a predetermined number of coefficient data items so as to produce a column vector output signal including a plurality of data items (y0, y1, y2, . . . , y7). In a first cycle, the leading data x0 of the column vector input signal is stored in a first store unit (Rin), whereas during this period of time, in a second cycle shorter in time than the first cycle, the data items (c0, c1, c2, . . . , c7) in the row direction constituting a first portion of the matrix are sequentially read out such that both data items are multiplied, thereby storing the multiplication results in an accumulator. A similar data processing is repeatedly executed so as to obtain, based on the outputs from the accumulator, a column vector output signal constituted by the plurality of data items (y0, y1, y2, . . . , y7).

High speed digital signal processor capable of achieving realtime

A plurality of external input information are added to a selecting circuit. The output of the selecting circuit is fed back as one of the external input information to the selecting circuit. The input signal groups are decoded, and are produced as control signals to specify the external input information in synchronism with clock signals. When the input select signal groups have the non-selection mode, the output that is fed back is necessarily selected.

Selecting means for selecting a plurality of information

Growing community of inventors

Hachioji, Japan

Yoshimune Hagiwara