Sharp Kabushiki Kaisha Corporation

Sharp Kabushiki Kaisha Osaka

Yoshimitsu Yamauchi

Naoki Ueda

Kenichi Tanaka

Keizo Sakiyama

Nobuhiko Ito

Yasuhiro Sugita

Kaoru Yamamoto

Fumiki Nakano

Masanori Yoshimi

Noritaka Kishi

Noboru Noguchi

Shigeo Onishi

Kengo Takahama

Shinichi Sato

Katsumi Fukumoto

Shigeo Ohnishi

Akitsu Ayukawa

Makoto Tanigawa

Hidehisa Tateoka

Kiyoshige Omori

Provided are a pixel circuit and a display device which support multi-gradation display and can prevent display quality from deteriorating with low power consumption. A pixel circuit () includes a first switch circuit () provided between a pixel node Np of a display element unit () and a data signal line SL, and a memory circuit () which restores the pixel node to an initial voltage state, based on a hold voltage stored in a storage node Nm. The memory circuit () includes a transistor Thaving a gate electrode connected to the storage node Nm, and a source electrode connected to the pixel node Np; a second switch circuit () which controls a conducting state between a drain electrode of the transistor Tand a voltage supply line VSL, in response to a signal level of a first control signal line SWL; a third switch circuit () which controls a conducting state between the drain electrode and the gate electrode of the transistor T, in response to a signal level of a second control signal line CSL; and a capacitor element Cst provided between the storage node Nm and the voltage supply line VSL.

Pixel circuit and display device

A pixel circuit includes: a light emitting element; an n-channel drive transistor Tthat has a source connected with an anode of the light emitting element, a gate connected with a pixel node, and controls a light emission current flowing in the light emitting element in accordance with a light emission control voltage between the gate and the source; a transfer transistor Twhich is interposed between a data signal line and the pixel node, and has a gate connected with a scan signal line; a control transistor Twhich is interposed between the source and a drain of the drive transistor T, has a gate connected with the scan signal line, and comes into an ON state simultaneously with the transfer transistor T; and a capacitance element which is interposed between the gate and the source of the drive transistor T, and holds the light emission control voltage.

An organic EL display device includes a controller, a data driver, and a DRAM which provides a gain correction memory and a threshold voltage correction memory. The data driver sends, to the controller, first and second measurement data Im corresponding to the first and second measuring data voltages Vm, respectively. The controller compares ideal characteristic data IO(P) with the first and second measurement data Im, and updates threshold voltage correction data Vt and gain correction data BR based on the comparison results. The controller corrects video data Vm based on the threshold voltage correction data Vt and the gain correction data BR. Thereby, both threshold voltage compensation and gain compensation of a drive transistor are performed with respect to each pixel circuit, while display is performed.

Display device and method for driving the same

Provided is a semiconductor memory circuit including an oxide semiconductor insulated gate FET enabling advanced performance without being affected by a variation in threshold voltage. A semiconductor memory circuit MC includes a first transistor element Tcomposed of an insulated gate FET having a gate electrode connected to a memory node N, a drain electrode connected to an intermediate node N, and a source electrode connected to a data I/O terminal DIO; a second transistor element Tcomposed of an oxide semiconductor insulated gate FET having a gate electrode connected to a first control terminal CIN, a drain electrode connected to the intermediate node N, and a source electrode connected to the memory node N; a capacitive element Chaving one end connected to a first voltage terminal VINand the other end connected to the memory node N; and a switching element Sfor controlling a conducting state between a second control terminal CINor a second voltage terminal VINor the first voltage terminal VIN, and the intermediate node N, based on a voltage level of at least the second control terminal CIN

Semiconductor memory circuit and device

Provided is a semiconductor storage device with which it is possible to write information to individual memory cells in which a storage node is configured with an oxide semiconductor insulated-gate FET source and a terminal of a capacitor element being connected. A storage node is configured by connecting a source of a first transistor to one terminal of a capacitor element. A drain of the first transistor and a source of a second transistor are connected to each other. A drain of the second transistor is a data input terminal. A first control terminal, which is formed by a gate of the first transistor being connected to another terminal of the capacitor element, is connected to a wordline, which extends in the row direction. A second control terminal, which is formed of a gate of the second transistor terminal, is connected to a write control line, which extends in the column direction. The storage node is connected to a gate of a third transistor, and a current flowing between a drain and a source of the third transistor is controlled according to a voltage level of the storage node.

Semiconductor storage device with two control lines

Provided is a semiconductor memory device including an oxide semiconductor insulated gate FET and having a capability to implement advanced performance without being affected by a variation in threshold voltage. A memory cell MC includes a memory node Nm formed at a connection point of a gate of a first transistor element T, a source of a second transistor element T, and one end of a capacitive element Cm, and a control node Nc formed at a connection point of a drain of the first transistor element Tand a drain of the second transistor element T. Each memory cell MC arranged in the same column includes the control node Nc connected to a shared first control line CL extending in a column direction, the first transistor element Thaving a source connected to a shared data signal line DL extending in the column direction, the second transistor element Thaving a gate connected to an individual first selection line WL, and the capacitive element Cm having the other end connected to an individual second selection line GL, and a switching element SE having one end connected to the first control line CL, and the other end connected to a voltage supply line VL is provided with respect to each first control line CL.

Semiconductor memory device

A display device in which low power consumption is realized without lowering an aperture ratio is provided. A liquid crystal capacitive element Clc is sandwiched between a pixel electrodeand an opposite electrode. The pixel electrode, one end of a first switch circuit, one end of a second switch circuitand a first terminal of a second transistor Tform an internal node N. The other terminals of the first switch circuitand the second switch circuitare connected to a source line SL. The second switch circuitis a series circuit composed of a first transistor Tand a diode D. A control terminal of the first transistor T, a second terminal of the second transistor Tand one end of a boost capacitive element Cbst form an output node N. The other end of the boost capacitive element Cbst and the control terminal of the second transistor Tare connected to a boost line BST and a reference line REF, respectively. The diode Dhas a rectifying function from the source line SL to the internal node N

Display device

A display device includes liquid crystal capacitor element formed between a pixel electrode and a counter electrode. One terminals of the pixel electrode, a first switch circuit, and a second switch circuit, and a first terminal of a second transistor form an internal node. The first switch circuit and the second switch circuit have other terminals connected to a source line. The second switch circuit is configured by a series circuit of transistors, and a control terminal of the transistor, a second terminal of the transistor, and one terminal of a boost capacitor element form an output node. The other terminal of the boost capacitor element is connected to a boost line, the control terminal of the transistor is connected to a reference line, and the control terminal of the transistor is connected to a selecting line.

A display device which realizes a multi-gradation constant display with low power consumption is provided. A pixel circuitincludes an internal node Nholding a pixel data voltage applied to a display element part, a first switch circuittransferring the pixel data voltage supplied from a data signal line SL to the internal node Nthrough a series circuit of first and second transistor elements Tand T, a second switch circuitincluding a third transistor element Tconnecting a middle node N, at which the first and second transistor elements Tand Tare connected, with a voltage supply line VSL, and a control circuitincluding a series circuit of a fourth transistor element Tand a first capacitive element C, holding the pixel data voltage held in the internal node Nat one end of the first capacitive element Cthrough the fourth transistor element T, and controlling on/off of the third transistor element Tby a boost voltage applied to the other end of the first capacitive element C

In a display device including a pixel circuit having a transistor with a low electron mobility, low power consumption is realized without decreasing an aperture ratio. An liquid crystal capacitor element (Clc) is formed between a pixel circuit () and a counter electrode (). One ends of the pixel electrode (), a first switch circuit (), and a second switch circuit () and a first terminal of a second transistor (T) form an internal node (N). The other end of the first switch circuit () is connected to a source line (SL). The second switch circuit () has the other end connected to a voltage supply line (VSL), and is a series circuit of transistors (Tand T). A control terminal of the transistor (T), a second terminal of the transistor (T), and one end of the boost capacitor element (Cbst) form an output node (N). The other end of the boost capacitor element (Cbst) and the control terminal of the transistor (T) are connected to a selecting line (SEL) and a reference line REF, respectively. A control terminal of the transistor (T) is connected to the selecting line (SEL) through a delay circuit ().

A liquid crystal display device is provided which is capable of sufficiently decreasing power consumption in permanent display of still images while keeping high quality display in transparent mode, in high resolution display panels. In each pixel circuit, a pixel electrode is connected to a source line via a third transistor. When a refreshing circuit performs a refreshing operation, a boosting signal line is supplied with a voltage pulse. If the pixel electrode is at a high voltage level at this time point, a voltage at a node is boosted and a first transistor turns ON to supply a reference voltage to the pixel electrode as a refreshing voltage. If the pixel electrode is at a low voltage level, there is no boost, and the first transistor stays in OFF state, so a node assumes a voltage which is given by an off-resistance ratio of the first and the third transistors, and this voltage is supplied to the pixel electrode.

A display device which can prevent deterioration of a liquid crystal and reduction in display quality at low power consumption without lowering an aperture ratio is provided. An opposite voltage (Vcom) is applied to an opposite electrode () of a liquid crystal capacitive element (Clc). One ends of a pixel electrode (), a first switch circuit (), a second switch circuit (), and a first terminal of a second transistor (T) form an internal node (N). The other ends of the first switch circuit () and the second switch circuit () are connected to a source line (SL) and a voltage supply line (VSL), respectively. A control terminal of a first transistor (T) in the second switch circuit (), a second terminal of the second transistor (T), and one end of a boost capacitive element (Cbst) form an output node (N). The other end of the boost capacitive element (Cbst) and the control terminal of the second transistor (T) are connected to a boost line (BST) and a reference line (REF), respectively. This configuration makes it possible to perform an action (self-refresh action) to return the absolute value of the voltage between both ends of a display element part to the value at the time of a last writing action without performing a writing action.

A display device which realizes constant display having multiple tones with low power consumption is provided. A pixel circuithas an internal node Nholding a pixel data voltage applied to a display element unit, a first switch circuittransferring the pixel data voltage supplied from a data signal line SL to the internal node Nthrough a series circuit of first and second transistor elements Tand T, a second circuithaving a third transistor element Twhich communicates between an intermediate node Nconnected with the first and second transistor elements Tand T, and a voltage supply line VSL, and a control circuitformed with a series circuit of a fourth transistor element Tand a first capacitative element C, holding the pixel data voltage held in the internal node Nat one end of the first capacitative element Cthrough the fourth transistor element T, and controlling conduction of the third transistor element Tby a boost voltage applied to the other end of the first capacitative element C, and the first and second transistor elements Tand Tare controlled individually.

In a display device, a liquid crystal capacitive element is sandwiched between a pixel electrode and an opposite electrode. The pixel electrode, one end of a first switch circuit, one end of a second switch circuit and a first terminal of a second transistor form an internal node. The other terminals of the first switch circuit and the second switch circuit are connected to a source line. The second switch circuit is a series circuit composed of a first transistor and a diode. A control terminal of the first transistor, a second terminal of the second transistor and one end of a boost capacitive element form an output node. The other end of the boost capacitive element and the control terminal of the second transistor are connected to a boost line and a reference line, respectively.

A display device where low power consumption is realized without lowering aperture ratio is provided. A liquid crystal capacitive element Clc is sandwiched between a pixel electrodeand an opposite electrode. The pixel electrode, one end of a first switch circuit, one end of a second switch circuitand a first terminal of a second transistor Tform an internal node N. The other terminals of the first switch circuitand the second switch circuitare connected to a source line SL and a voltage supply line VSL, respectively. The second switch circuitis a series circuit including a transistor Tand diode D. A control terminal of the transistor T, a second terminal of the transistor Tand one end of a boost capacitive element Cbst form an output node N. The other end of the boost capacitive element Cbst and the control terminal of the transistor Tare connected to a boost line BST and a reference line REF, respectively. The diode Dhas a rectifying function from the voltage supply line VSL to the internal node N

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Osaka, Japan

Yoshimitsu Yamauchi