Hitachi, Ltd.

Hitachi-high-technologies Corporation

Yoshimichi Sato

Nobuyasu Kanekawa

Shoji Suzuki

Mitsuji Ikeda

Shinya Ohtsuji

Hiroshi Sato

Makoto Nohmi

Korefumi Tashiro

Keisuke Bekki

Yuichi Abe

Yasutaka Toyoda

Fumihiro Sasajima

A pattern matching method for a scanning electron microscope comprises a step of performing pattern matching of only an upper layer pattern between an image () in which a pattern consisting of plural layers is represented and a template () in which the upper layer pattern of the plural layer pattern is selectively represented, thereby identifying the position of the pattern consisting of the plural layers. Then, information about the upper layer pattern is subtracted from the image (), thus extracting shape information () about the lower layer pattern. Consequently, stable positioning or selective information extraction on a certain layer is enabled regardless of the state of the depths of a pattern formed in three dimensions or of the charge state of a sample.

Pattern matching method and image processing device

The present invention provides a unified template matching technique which allows an adequate matching position to be provided even in an image with a distorted pattern shape and a variation in edge intensity. A correlation value contribution rate map is created for the vicinity of each of top candidate positions obtained by applying a centroid distance filter to a normalized correlation map resulting from template matching. A corrected intensity image is created from the correlation value contribution rate maps. Luminance correction is performed based on the corrected intensity image. Local matching is performed again on the vicinity of each candidate position. The candidates are then re-sorted based on candidate positions and correlation values newly obtained. Thus, even in an image with a distorted pattern shape and a variation in edge intensity, an adequate matching position can be provided in a unified manner.

Image inspection apparatus

The present invention achieves the process of easily registering a template which is prepared for a size change in pattern matching for specifying a measurement point, and high-speed pattern matching by which adequate position accuracy can be obtained in measurement. The present invention includes means for automatically calculating the size and position of a positioning template different from a measurement point itself when the measurement point is designated, to display a template having the calculated size and position. The present invention further includes means for performing pattern matching by using all or some of a plurality of divided templates and extracting templates having a similar positional relationship to the original positional relationship.

Image processing system and scanning electron microscope

An inspection apparatus and method outputs an accurate matching position even if a search image contains a pattern similar to a template. An image search unit includes a relative position comparing unit which compares the relative position of a template in a template selection image with the relative position of a location currently being searched for in a search image and outputs the amount of position mismatch between the relative positions. A matching position determining unit determines a matching position by taking into consideration the amount of position mismatch in addition to search image similarity distribution information.

Image processing method for determining matching position between template and search image

A self-checking circuit, which is useful for a highly reliable system configuration, includes a logic circuit having an error detection function. For function blocks for feeding out a plurality of signals that are at least duplexed, the logic circuit compares the output signals of the function blocks, and detects an error on the basis of results of the comparison. The logic circuit comprises synthesizing means provided to superimpose inherent waveforms assigned in advance to the respective output signals of the function blocks onto the output signals of one of the function blocks. The inherent waveforms are orthogonal waveforms generated by an orthogonal waveform generator circuit. The logic circuit also comprises comparison means for comparing a signal output of the synthesizing means with the signal output of the other function block to detect an error. The whole circuit including the function blocks are judged normal only if the waveforms inherent to both output signals exist.

Logic circuit having error detection function, redundant resource management method, and fault tolerant system using it

Logic circuit having error detection function, redundant resource

A self-checking circuit, which is useful for a highly reliable system configuration, includes a logic circuit having an error detection function. For function blocks for feeding out a plurality of signals that are at least duplexed, the logic circuit compares the output signals of the function blocks, and detects an error on the basis of results of the comparison. The logic circuit comprises synthesizing circuitry provided to superimpose inherent waveforms assigned in advance to the respective output signals of the function blocks onto the output signals of one of the function blocks. The inherent waveforms are orthogonal waveforms generated by an orthogonal waveform generator circuit. The logic circuit also compares the output signals having the superimposed inherent waveforms with the signal output of the other function block to detect an error. The whole circuit including the function blocks are judged normal only if the waveforms inherent to both output signals exist.

The same electrical device can be used in two modes, a simplex bus connection mode and a duplex bus connection mode, by collating signals output from two input and output ports for two electrical circuits in an electrical device with a comparator and detecting a fault in the electrical circuits in a duplex bus connection mode, and by checking whether a normal signal is output from an input and output port by collating a signal output from one input and output port for one of the two electrical circuits with the output signal fed back via another input and output port in a simplex bus connection mode.

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Hitachi, Japan

Yoshimichi Sato