Seiko Epson Corporation

Yoshimi Oka

Nobuyuki Saito

Daisuke Sato

Hironobu Kazama

Kenyou Nagao

A data transfer control device including: a buffer controller which allocates a plurality of pipe regions in a packet buffer and controls access to the packet buffer; and a transfer controller which controls data transfer between the pipe regions and corresponding endpoints. The transfer controller performs processing of pausing data transfer between the pipe regions and the endpoints, the buffer controller performs reconstruction processing which includes at least one of deletion, addition, and size change of the pipe regions after the completion of the pause processing, and then the transfer controller resumes the paused data transfer after the reconstruction processing of the pipe regions. Data in the pipe regions before the reconstruction processing is copied to the pipe regions after the reconstruction processing while preventing the data from being erased.

Data transmission controller that restarts data transmission when reconstruction is completed

Data to be transferred from a BUS(IEEE 1394 or USB) is encrypted by a second encryption process (DES) and the encrypted data is written to an external SDRAM through an external terminal of a data transfer control device. The encrypted data that has been written to the SDRAM is read through the external terminal, and the thus-read encrypted data is transferred to a BUSto which an HDD is connected. Encrypted data transferred from the BUSis decrypted by a first decryption process (DTCP), and is written to a small-capacity SRAM within the data transfer control device. The thus-written decrypted data is read from the SRAM and encrypted by the second encryption process. Paths that bypass the second encryption (or decryption) are also provided.

Data transfer control device, electronic instrument, and data transfer control method

A data transfer control device includes a DMACthat writes a packet transferred from a BUS(IEEE 1394 or USB), to a SRAM, a DMACthat reads the written isochronous data from the SRAM and writes it to a SDRAM, and a DMACthat reads the written isochronous data and transfers it to a BUSside. During transmission, isochronous data is read from the SDRAM and written to SRAM, and an isochronous packet including the written isochronous data is transferred to the BUSside. The SRAM includes an isochronous data area and an asynchronous data area. The SRAM is provided insides the data transfer control device and the SDRAM is provided on outside the data transfer control device.

A processing section reserves a number of transfers for an isochronous packet which includes isochronous data in an transfer number reservation register TNREG. A DMACreads that isochronous packet from SRAM, and the thus-read isochronous packet is transferred automatically to a BUS(IEEE 1394 or USB) side at each isochronous transfer cycle until the number of transfers reserved in TNREG reaches zero. An SRAM header area is divided into page K and page L areas, and registers TNREGK and TNREGL are provided for reserving a number of transfers for each of the page K and L areas. During a special reproduction, a data pointer is used to select a TS packet which includes an I picture, for automatic transfer to the BUSside.

Growing community of inventors

Kitahiroshima, Japan

Yoshimi Oka