Nec Corporation

Renesas Electronics Corporation

Yoshimi Matsumoto

Hideyuki Takahashi

A power supply control method of performing a feedback control of an output voltage based on a deviation signal for a standard voltage value serving as a target value for the output voltage and a digital signal generated by analog/digital (A/D) conversion of the output voltage, the method includes selecting a range of the reference voltage for the A/D conversion based on the digital signal in a power supply startup period, and selecting a range of the reference voltage for the A/D conversion based on the deviation signal or a signal corresponding to the deviation signal in a steady state period.

Power supply controller having analog to digital converter

A power supply controller includes a switching circuit which, in response to a control signal, transfers an analog signal to an output node as an outputted analog signal, the output node being coupled to an inductor and a capacitor, an analog to digital (A/D) converter which converts an outputted analog signal to a digital signal, a pulse width modulation (PWM) generator circuit which produces a PWM signal based on the digital signal, a driver which produces the control signal in response to the PWM signal, and a conversion range setting unit which sets a range data for the A/D converter based on the digital signal during a first period, and which sets the range data based on the PWM signal during a second period.

A power supply controller includes an analog to digital (A/D) converter that performs analog-digital conversion of an output voltage and outputs a digital signal, a deviation signal generator unit that generates a deviation signal from the digital signal and a standard voltage value serving as an output voltage target value, and a power controller unit that controls the output voltage based on the deviation signal. The power supply controller includes a conversion range setting unit that sets a range of the reference voltage into the A/D converter based on a first signal as the digital signal in a power supply startup period, and sets the reference voltage range into the A/D converter based on a second signal as the deviation signal or as a signal corresponding to the deviation signal in a steady state period.

A parallel-to-serial data conversion circuit includes a control circuit receiving a load signal, a clock signal and high-order 4 bits of a parallel data of 8-bit PCM code excluding the MSB bit, for generating a first control signal and a second control signal, a 6-bit shift register receiving the first control signal, the second control signal, low-order 4 bits of the parallel data, a store signal and the clock signal, and a selector for selecting the output of the shift register on the basis of the MSB bit and the first control signal.

Parallel-to-serial data conversion circuit

A parallel-serial data converter according to the present invention comprises a n-th latch circuit which latches the sign bit at the most significant bit of parallel data, a n-1th selector which selects either of the n-1th bit or the ground level, a n-1th latch circuit which latches the output from the selector n-1, a i-th selector which selects either of the i-th bit (i=n-2, n-3, . . . , 2, 1) of the parallel data or the output from the i+1th latch circuit, a i-th latch circuit which latches the output from the i-th selector, a n-th selector which selects either of the output from the first inverter to reverse the output from the first latch circuit or the output from the first latch circuit, a n+1th selector which selects either of the output from a second inverter to reverse the output from the n-th selector or the output from the n-th selector for output as serial data in two's complement notation, a set latch circuit which is set according to the STORE signal and latches the output from the first AND circuit to take the logical AND the output form the n-th selector and the selection signal as well as a second AND circuit which takes the logical AND the output from the set latch circuit and the output from the n-th latch circuit for output as the selection signal.

Parallel-serial data converter

An interface circuit capable of performing an exact data transfer between two devices operated by asynchronous two clocks of the same frequency even when the clock contains a jitter, including three-stage latches coupled by a cascade connection and a control circuit to output a one-shot pulse when one external clock and one internal clock are input. The first latch latches input data by the external clock, the second latch latches the data output from the first latch by the pulse of the control circuit, and the third latch latches the data output from the second latch by the internal clock and outputs the data. The input data are output from the third latch in the input order without a continuous or repeated output of the same data or an omission or deletion of the output data.

Growing community of inventors

Kanagawa, Japan

Yoshimi Matsumoto