Oki Electric Industry Co., Ltd.

Oki Semiconductor Co., Ltd.

Lapis Semiconductor Co., Ltd.

Yoshimi Egawa

Shinji Ohuchi

Noritaka Anzai

Kazumi Shinchi

Takeshi Niigaki

Yasufumi Uchida

Harufumi Kobayashi

Akira Sugai

A method for manufacturing a printed circuit board having an insulative board and a plurality of electroconductive pads arranged in a grid shape on the insulative board, the method including a step for forming an electroconductive film on the insulative board; a step for forming a pattern on the electroconductive film so as to form the electroconductive pads, a lead wire connected to at least one of the electroconductive pads, and inter-pad wiring for electrically connecting each of the electroconductive pads not connected to the lead wire to any of the electroconductive pads connected to the lead wire, the inter-pad wiring being disposed between mutually adjacent electroconductive pads; a step for plating each of the electroconductive pads by immersing the insulative board in a plating bath and energizing each of the electroconductive pads through the lead wire; and a step for removing the inter-pad wiring.

Method for manufacturing printed-circuit board

A method of manufacturing a semiconductor device which can reduce the number of times of resin-injection, thereby facilitating the miniaturization of the semiconductor device, and the semiconductor device. After resin is injected into a space between at least two second semiconductor chips flip-chip joined to a first semiconductor chip through an injection opening, the resin is hardened.

Method of manufacturing semiconductor device and the semiconductor device

A semiconductor package includes a wiring board; a first electrode for external connection; a ball pad; a semiconductor chip; a mold resin; an electrode unit connected with the ball pad and penetrating the mold resin; and a second electrode for external connection connected with a portion of the electrode unit on a side of an outer surface of the mold resin. The electrode unit includes a first ball disposed on the ball pad; a second ball disposed between the first ball and the second electrode; and a solder material connecting between the ball pad and the first ball, between the first ball and the second ball, and between the second ball and the second electrode for external connection; each of the first ball and the second ball including a core part having a glass transition temperature which is higher than a melting point of the solder material.

Semiconductor package and package-on-package semiconductor device

There is provided a method of manufacturing a camera module including a sensor package having an image pickup element, and a lens configuration in which a lens holder, and a receptacle accommodating the sensor package are integrally formed, the sensor package being fixed within the receptacle, the method including: applying a photo-curing resin to predetermined portions of the receptacle; performing alignment of a relative position of the sensor package to the lens configuration; a first joining whereby the photo-curing resin is cured so that the sensor package is fixed within the receptacle while maintaining the relative position of the sensor package to the lens configuration; and a second joining whereby a thermosetting resin is applied so as to fill a space formed between the sensor package and the lens configuration, and then curing the thermosetting resin.

Camera module and method of manufacturing camera module

A semiconductor device having a semiconductor substrate including a first surface and a second surface corresponding to a back surface with respect to the first surface and having first through electrodes which extend through the first surface and the second surface, semiconductor chips which are mounted over the first surface of the semiconductor substrate and each of which is constituted of a material of the same kind as the semiconductor substrate and has a circuit element electrically connected to the first through electrodes, stress relaxing sections which are provided with first conductors formed over the second surface of the semiconductor substrate and electrically connected to the first through electrodes of the semiconductor substrate and having flexibility, and external connecting terminals provided over the stress relaxing sections and connected to the first conductors respectively.

Semiconductor device having stress relaxation sections

A method for manufacturing a semiconductor device includes the steps of (a) preparing a wafer including a first circuit formation region and a first surrounding region, (b) laminating a first chip on the first circuit formation region, (c) pouring a first underfill into a first space between the first circuit formation region and the first chip from the first surrounding region, (d) hardening the first underfill, (e) forming a laminated structure comprised of a first chip block that includes a second chip including the first circuit formation region, the first chip, and the first underfill by conducting dicing with respect to the wafer; and (f) laminating the laminated structure on a substrate.

Method for forming laminated structure and method for manufacturing semiconductor device using the method thereof

A through electrode extends through a silicon substrate from the upper surface to the lower surface of the substrate to accomplish electrical conduction between the upper and lower surfaces of the substrate. The through electrode includes a plurality of slender through holes formed in a through electrode forming area of the silicon substrate. The slender through holes extend through the silicon substrate from the upper surface to the lower surface of the silicon substrate. The through electrode also includes a plurality of conductive bodies fitted in the slender through holes. The conductive bodies are electrically connected with each other.

Semiconductor device having a package base with at least one through electrode

A semiconductor package according to the present invention includes a substrate; first and second semiconductor chips mounted on a first surface of the substrate; and a heat-radiation sheet. The heat-radiation sheet includes a heat-transferable conductive layer and first and second insulating layers formed on top and bottom surfaces of the heat-transferable conductive layer, respectively. The heat-radiation sheet includes a first portion arranged between the first semiconductor chip and the second semiconductor chip; and a second portion extending at least a side of the first portion. The second portion is connected to the substrate. The second insulating layer of the second portion is formed to expose a part of the heat-transferable conductive layer.

Semiconductor package

To improve the fabrication yield of semiconductor devices. A semiconductor device where a desired number of semiconductor chips are laminated in the thickness direction thereof is fabricated by repeating, an arbitrary number of times such as one time or two or more times, a step of bonding and mounting another support substrate laminate on first bumps exposed by separating and removing one support substrate from a support substrate laminate composite where second bumps of two support substrate laminates including plural semiconductor wafers mounted on support substrates have been made to face each other and are electrically connected.

Semiconductor device fabricating method

According to this invention, a method for fabricating a semiconductor package, in which a plurality of semiconductor chips having a through electrode is layered on a semiconductor interposer, comprising: mounting and layering a plurality of semiconductor chips on a first surface of a semiconductor wafer, which is to be used for a semiconductor interposer; forming a mold resin over the semiconductor chips to cover the semiconductor chips entirely; and dicing the semiconductor wafer to form a plurality of individual semiconductor packages.

Method for fabricating semiconductor package

In a semiconductor device having a semiconductor chip mounted on a printed circuit board, the semiconductor chip has a plurality of electrodes and the printed circuit board has a plurality of conductive patterns. Metallic plated layers are formed on the electrodes of the semiconductor chip. The metallic plated layers on the electrodes of the semiconductor chip are electrically connected with the conductive patterns of the printed circuit board by metallic wires.

Semiconductor device and manufacturing method thereof

A multi chip package includes a substrate; a first semiconductor chip mounted on the substrate; a second semiconductor chip mounted above the first semiconductor chip; a first bonding wire electrically coupled to a first bonding pad on the first semiconductor chip; and a second bonding wire electrically coupled to a second bonding pad on the second semiconductor chip. At least the first bonding wire is of a coated wire, which comprises a conductive core and an outer insulation coating. At least the first bonding pad is of a multi layered pad, comprising a base pad formed on the first semiconductor chip; a first conductive layer formed on the base pad; and a second conductive layer formed on the first conductive layer.

Multi chip package

A stacked multi-chip package includes a substrate, a first chip and a second chip. The first chip is fixed to the substrate, and is provided with a collar portion which opposes an upper face of the substrate in a state such that a gap is formed between the upper face of the substrate and the collar portion. The second chip is disposed in a region below the collar portion. The second chip is fixed to the substrate and does not make contact with the first chip.

Fabrication method for stacked multi-chip package

A semiconductor device includes a substrate, and a recess is formed in the substrate. A back surface of the substrate is covered with an insulating film, and wiring, pads and posts are formed on the insulating film. The pads are connected to the posts by the wiring. The entire back surface of the substrate except for areas of the pads and the posts is covered with the insulating film. External terminals, such as solder balls, are formed on the posts. A first chip is fixed to the pads within the recess, and a second chip is adhered to the first chip with an adhesive. The first chip and the second chip respectively have a wafer level chip size package (WCSP) structure where external terminals are arranged planarly by rewiring from internal electrodes which are provided with an insulating coating.

Growing community of inventors

Tokyo, Japan

Yoshimi Egawa