Fujitsu Corporation

Yoshimi Asada

Tatsumi Nakada

When a selector selects a first input terminal, a first loop circuit is formed including first and second input buffer circuits and an output buffer circuit. When the selector selects a second input terminal, a second loop circuit is formed including the first input buffer circuit and the output buffer circuit. When the selector selects a third input terminal, a third loop circuit is formed including the first input buffer circuit, a variable delay line (VDL), and the output buffer circuit. From the oscillating frequencies of loop circuits each formed as a ring oscillator, their respective signal delay times are obtained. By equalizing characteristics of first and second input buffer circuits, through a mutual operation using the signal delay times of respective loop circuits, a propagation delay time over a timing signal supply path including the first input buffer circuit and the VDL and stretching to a flip-flop is obtained precisely.

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Kawasaki, Japan

Yoshimi Asada