Matsushita Electric Industrial Co., Ltd.

Yoshimasa Obayashi

Kenichi Kawaguchi

Yoshiteru Mino

Katsuyuki Kaneko

Ikuko Fujinawa

Kouichi Iwamori

Sadafumi Tomida

Even if a plurality of tasks that access a plurality of data areas each having the different control method are operated in parallel and the access requests are generated almost simultaneously, the simultaneous accesses to the memory device can be prevented and also a plurality of tasks can be operated in parallel while maintaining a real-time characteristic since the access request contained in the tasks are divided into partial request units by the access-request mediating portion to switch the access requests.

Memory device control system

When the use of a receiver the bus is not be acquired in delayed read or posted write, the length of a burst data transfer is limited by the capacity of the buffer in a bridge device. In order to solve this problem, waits are inserted in data output process via a sender bus in delayed read or posted write according to the condition of the receiver bus. As a result, input rate of data into the buffer in the bridge device is kept constant, and the use of the receiver bus can be acquired in the delayed read or the posted write. Data is simultaneously transferred into and from the buffer in the bridge device, so that the probability of burst data transfer with a long burst data transfer length is increased.

Bridge device that prevents decrease in the data transfer efficiency of

One block of non-zero coefficients obtained through the decoding of the entropy decoding unit 2024 is stored in the coefficient storage unit 121 in accordance with positional coordinates calculated by the non-zero coefficient scanning order calculation unit 2023a and the non-zero coefficient position conversion unit 2023b. The stored non-zero coefficients are then inverse quantized by the inverse quantization unit 2022. The non-zero coefficient range calculation unit 122 specifies a region of the coefficient storage unit 121 in which the non-zero coefficients are stored. The calculation order control unit 123 controls the inverse DCT unit 2021 to only perform an inverse DCT (discrete cosine transform) for non-zero coefficients located in the specified region.

Apparatus for decompressing image data which has been compressed using a

The present invention discloses processor elements interconnected via a network in a parallel computer. The processor element includes a memory unit for storing a program and, per array-variable name, a partitioned array variable, the program being run simultaneously by the processor elements, each partitioned array variable being allocated to respective processor elements, a processor for carrying out a calculation using the partitioned array variable in the memory unit, the partitioned array variable being accessed by being addressed with a variable-name address that includes a code representing an array-variable name, an address converting unit for holding a variable-name address in relation with a physical address on the memory unit for each partitioned array variable to output a corresponding physical address in response to an input of the variable-name address from the processor, a transferring unit for transferring an array variable per array-variable name with the other processor elements via the network, the array variable being transferred to be stored into a free area acquired in the memory unit when a partition direction changes, the free area being as large as a storage area for one partitioned array variable, an address-correspondence updating unit for updating an address correspondence in the address converting unit with a pre-transfer variable-name address in relation with a post-transfer physical address each time the transferring unit completes the transfer per array-variable name.

Growing community of inventors

Kyoto, Japan

Yoshimasa Obayashi