Sanyo Semiconductor Co., Ltd.

Sanyo Electric Co., Ltd.

Semiconductor Components Industries, LLC

Yoshimasa Amatatsu

Hirotsugu Hata

Mitsuru Soma

Katsuya Okabe

Minoru Akaishi

Satoshi Onai

Yoshiaki Sano

Akira Yamane

In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.

Semiconductor device and method of manufacturing the same

A conventional semiconductor device has a problem that reduction of a connection resistance value between wiring layers is difficult because of an oxide film formed between the wiring layers. In a semiconductor device of this invention, a first metal layer is embeded in opening regions which connect a first wiring layer and a second wiring layer and an opening is formed in a spin coated resin film formed on the first metal layer. In the opening, a Cr layer forming a plating metal layer and a Cu plated layer are connected to each other. With this structure, the spaces among crystal grains in portions in the Cr layer on the first metal layer are wide, which causes the portions to be coarse. In the coarse portions in the Cr layer, an alloy layer formed of the second metal layer and the Cu plated layer is formed, and thus, the connection resistance value is reduced.

Semiconductor device and manufacturing method of the same

In a semiconductor device according to the present invention, a plurality of opening regionstoare formed in an insulating film on a pad electrode. A metal layerformed on the pad electrodehas a plurality of concave portionstoformed therein by covering the opening regionsto. Moreover, in a peripheral portion at a bottom of each of the concave portionstoin the metal layer, the metal layerand a Cu plating layerreact with each other. By use of this structure, the metal reaction area serves as a current path on the pad electrode. Thus, a resistance value on the pad electrodeis reduced.

Semiconductor device and manufacturing method thereof

In a semiconductor device according to the present invention, two epitaxial layers are formed on a P type substrate. In the substrate and the epitaxial layers, isolation regions are formed to divide the substrate and the epitaxial layers into a plurality of islands. Each of the isolation regions is formed by connecting first and second P type buried layers with a P type diffusion layer. By disposing the second P type buried layer between the first P type buried layer and the P type diffusion layer, a lateral diffusion width of the first P type buried layer is reduced. By use of this structure, a formation region of the isolation region is reduced in size.

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Gunma, Japan

Yoshimasa Amatatsu