Matsushita Electric Industrial Co., Ltd.

Yoshikuni Shindo

Takahisa Hatano

Hirokatsu Yui

Hiromitsu Torii

Taro Funamoto

Kazuhiro Yamada

Kazunari Yamaguchi

Hideki Abe

Kazushige Kida

Noriyuki Iwakura

Fumlou Kameoka

Fumiou Kameoka

The invention relates to a multiscanning type display apparatus having a matrix drive type display device for displaying picture signals, a picture signal supplying section for supplying picture signals to the display device, a synchronization signal supplying section for outputting synchronization signals included in the above mentioned picture signals, and a resolution power converting section for converting the resolution of the above mentioned picture signals to the resolution of the above mentioned display device.

Multiscanning type display apparatus

A video display device for displaying a wide range of video signals which allows the user to freely set the screen display width and position. A request for adjusting the horizontal display width, vertical display width, horizontal display position, and vertical display position is made through a key circuit, and a microcomputer determines the state of the key circuit. The microcomputer then recalculates the horizontal expansion rate and vertical expansion rate of a scan converter, and send recalculated data to the scan converter and a PLL circuit. The scan converter and the PLL circuit converts signals to the number of picture elements displayable on the video display device in response to a request for adjustment, and changes the phase of the enable signal which indicates a display period of the video display device to adjust horizontal and vertical display positions.

Width adjustment circuit and video image display device employing thereof

A/D converters (,), a PLL circuit (,), a scan conversion circuit (,), counters (,and,), an OR circuit (,), flip-flops (,) for comparing a phase of an output signal from the OR circuit (,) with a phase of an enable signal, and a CPU (,) are provided in a LCD apparatus so that settings in the scan conversion circuit (,), counter (,and,), and PLL circuit (,) can be changed responsive to outputs from the flip-flops (,), whereby a location and a size of a picture displayed on the LCD as well as a sampling clock frequency used in the A/D conversion can be automatically adjusted.

Liquid crystal display apparatus

The invention presents a dot clock reproducing apparatus for automatically reproducing the dot clock easily, by setting the dot clock frequency of a video signal source, and correcting the phase difference of the dot clock occurring in the transmission route or the like, and also presents a dot clock reproducing method comprising, in dot clock reproduction, a step of sampling at a frequency different from the dot clock of video signal, a step of detecting the aliasing frequency component occurring at this time, and a step of reproducing the dot clock so as not to cause this aliasing frequency component, and as an apparatus employing such method, the invention further provides a dot clock reproducing apparatus comprising A/D converting means for receiving an adjusting signal delivered from a video signal source, and sampling this adjusting signal to convert into a digital signal, PLL means for dividing a specified synchronizing signal and generating a sampling clock for the A/D converting means, frequency analyzing means for analyzing the frequency of the adjusting signal from the output of the A/D converting means, and dividing ratio setting means for controlling the dividing ratio of the PLL means from the output of the frequency analyzing means, wherein the dot clock is reproduced so that the output of the PLL means may be used as the dot clock signal, thereby realizing a dot clock reproducing apparatus for reproducing automatically the dot clock easily, by setting the dot clock frequency of the video signal source, and correcting the phase difference of the dot clock occurring in the transmission route or the like.

Dot clock reproducing method and dot clock reproducing apparatus using

A video display monitor employs interpolation which maintains sharpness in images which have large differences in signal levels of picture elements and assuring smoothness of images such as lamps which have small differences in signal levels. The difference in the signal level differences of respective adjacent picture elements is detected by delay and subtraction. A decoder produces a signal for interpolation based on the input of an interpolation coefficient and the absolute value of the interpolation coefficient which is output from an absolute value detector.

Video display monitor employing image interpolation

A pixel conversion apparatus includes a sync separator for separating a sync signal from an input signal, a pixel conversion information analyzer for analyzing how to convert the number of pixels to display the input signal as an image from the input signal and a picture display area, a timing signal generator for generating a timing signal for displaying an image according to the outputs of the sync separator and the pixel conversion information analyzer, a pixel converter for processing a pixel conversion of the input signal according to the output of the timing signal generator, an interpolator for processing a pixel interpolation when the pixel to be interpolated generated by pixel conversion at the pixel converter, and a sync signal generator for generating a sync signal for displaying the input signal as an image. Because the relation between the input signal and the image display area is previously analyzed and processed, there is no lack, or display by mistake, of image information included in the input signal and a high quality image can be effectively displayed on the picture display area of the display device.

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Sapporo, Japan

Yoshikuni Shindo