Hitachi, Ltd.

Yoshiko Tamaki

Yasuhiro Inagami

Katsuyoshi Kitai

Teruo Tanaka

Tadayuki Sakakibara

Yoshikazu Tanaka

Shigeo Nagashima

Tadaaki Isobe

Masanao Ito

Yuji Tsushima

Shigeko Yazawa

Shigeko Hashimoto

Kentaro Shimada

Naoki Hamanaka

Takayuki Nakagawa

Naonobu Sukegawa

Hiroaki Fujii

Yonetaro Totsuka

Isao Watanabe

Hisashi Katada

Taisei Yoshino

Tadayuki Sakakibaraa

A high-speed performance simulation method and system for simulating the performance of a large-scaled system such as a parallel computer. In implementation, the large-scaled system is divided into subsystems or partial units and the divided subsystems are simulated in parallel. Even when a particular partial unit occupies a shared resource, high-speed, well-coordinated performance simulation is achieved. A performance simulation system includes a plurality of performance simulators and an overall control section connected to these performance simulators. The plurality of performance simulators individually simulate the performances of partial units into which a simulant is divided. The overall control section causes the performance simulators to conduct the simulation processes alternately every AT cycle. When having finished a performance simulation process for a AT cycle, the first performance simulator transmits to the second performance simulator shared resource data stored in a shared resource management section, the shared resource occupation status data indicating that the shared resource is occupied. Then, the second performance simulator conducts a performance simulation process for a AT cycle and transmits shared resource occupation status data to the first performance simulator. The performance simulators responsible for subsystems that have no shared resource conduct simulation processes concurrently to increase the whole simulation speed.

Method and system for simulating performance of a computer system

Each small instruction in a VLIW instruction (long instruction) is added with the number of NOP instructions which succeed the small instruction, and these NOP instructions are deleted from the succeeding long instruction. A plurality of long instructions are therefore time-compressed. Thereafter, a plurality of small instructions in each long instruction are divided into a plurality of groups, and a combination of operation codes (OP codes) of small instructions in each group is replaced by a group code to generate a compressed, grouped instruction. Each long instruction is therefore space-compressed. An instruction expanding unit has an instruction expanding circuit for each grouped instruction. Each instruction expanding circuit expands one grouped instruction in a long instruction, generates a group of small instructions represented by the grouped instruction, and supplies the group of generated small instructions to respective function units via a decode unit. In this case, each instruction expanding circuit supplies after each small instruction NOP instructions same in number as that designated by a NOP number associated with each small instruction in this grouped instruction.

Processor for VLIW instruction

To realize interprocessor data transfer with the data receive area not fixed in the real memory and with less overhead for synchronization, the send node sends to the destination node, data, a virtual address of a receive area, an address of a receive control flag, a comparison value, and a comparison method. Network adaptor in the destination node judges whether the transfer condition is fulfilled, based on the comparison value, the comparison method and the semaphore in the receive control flag designated by the receive control flag address. Network adaptor further detects whether the receive area of the virtual address is in the main storage, based on the virtual address and the address translation table. The send data is stored in the receive buffer provided in the area for OS, when the above-mentioned condition is not fulfilled or the receive area is not in the main storage. Either when the destination node program issues a specific system call or when the program issues a reading instruction to the data in the receive area and a page fault is generated, OS moves the send data from the receive buffer to the receive area.

Method of interprocessor data transfer using a network, virtual

A method and apparatus for handling a large-capacity register file by using a small instruction field as to support a software pipeline. The invention includes a register file having a plurality of physical registers corresponding to a plurality of physical register numbers and a converter which converts logical register numbers included in instructions to be executed into physical register numbers. A physical register, which is used when a logical register is accessed as a result of execution of an instruction, is specified by a pointer corresponding to the logical register number included in the instruction. The pointer used for the access is incremented if so specified in the instruction to ensure that subsequent instructions making access to the same logical register use different physical registers.

Processor having a register configuration suited for parallel execution

In a multiprocessor computer system, individual vector processors are provided with priority switching signal control circuits, respectively, and a storage control unit incorporating a priority control circuit. Priority bit information is provided for priority circuits incorporated in the storage control unit. Paths for priority switching signal issued in accordance with a number of requests as generated and types of instruction generating the requests are provided between the priority switching signal control circuits and the priority control circuit of the storage control unit, while paths for the priority switching signal as generated are provided between the priority control circuit and all the priority circuits.

Priority control with concurrent switching of priorities of vector

In order to make use of row address lock mode of operation of a plurality of memory banks comprising synchronous DRAMs or the like and divided into a plurality of real bank groups, for example, for example, more than the memory banks are grouped into a plurality of logical groups each spanning the real bank groups. Addresses are allocated in unit of each logical group in a block-interleaving manner. When a series of requests issued by a given requester include a plurality of requests for accessing the same row address in the same memory bank, that requester requests that the row address be locked for access by the plurality of requests. The lock request is retained by a row address management unit. When a succeeding request from another requester requests access to a row address other than the locked address in the same memory bank, a priority circuit selects a predetermined number of requests from the initial requester having locked the memory in preference to a request made by the other requester.

Processor system having address allocation and address lock capability

Preload register groups are respectively provided for the plurality of scalar processors which execute iterative processing in distributed manner. Each group consists of preload registers corresponding to a plurality of data arrays that appear in the iterative processing. According to address information about the plurality of arrays to be preloaded specified by any of the processors, a preload control unit reads partial data groups of one of the arrays to be first processed by all of the processors from the main storage in parallel. Then, the same operation is performed on another array. Subsequently, in the above-mentioned manner, remaining elements of the arrays are read from one array to another. A partial element group thus read sequentially is stored in the plurality of preload register groups in distributed manner. According to a load request issued from each processor, the array elements preloaded in the preload register groups corresponding to that processor are read in the order the array elements were preloaded.

Data processor system for preloading/poststoring data arrays processed

Interprocessor priority control system for multivector processor

A vector processor includes a storage control apparatus which incorporates an access request buffer unit equipped with an address decoding unit having address decoder circuits corresponding to all models of the vector processors belonging to a same machine series. By using model ID signals, the address decoding is selectively enabled by a selector. The address decoding unit equalizes the periodicities at which the address assignments to the memory modules are skewed or shifted for all the element parallelism factors of the processors belonging to the same machine series. Access request queue is provided in a necessary number of stages in precedence to an access request priority determining unit incorporated in the storage control apparatus.

Vector processor adopting a memory skewing scheme for preventing

A vector processor system for processing vector instructions and scaler instructions fetched from storages includes a memory storage, a first and a second scaler processing units connected to the memory storage, a vector processing unit being connected to the memory storage and the two scaler processing units and for processing a vector instruction fetched from the memory storage during processing of scaler instruction/vector instruction separate type programs and a vector instruction received from the second scaler processing unit during processing of scaler instruction/vector instruction mingled type programs. More particularly, for scaler instruction/vector instruction mingled type programs, the vector processing unit receives the vector instruction from the scaler processing unit, whereas for scaler instruction/vector instruction separate type programs, the vector processing unit retrieves the vector instruction directly from the memory storage.

Vector processing apparatus for processing different instruction set

In a multiprocessor system having a plurality of main memories and a shared extended memory, each main memory is associated with an extended memory partial write control. When an extended memory partial write instruction is issued, tag information identifying updated portions of main memory data is transferred to the associated extended memory partial write control along with the main memory data. Each time a subblock of the main memory data arrives, the extended memory partial write control performs a partial write operation to substitute those portions of the main memory data which are identified by the tag information for the corresponding portions of a data subblock in a specified extended memory area. During this partial write operation, that specified extended memory area is kept locked.

Method and apparatus for parallel processing of a large data array

Each processor of a multiprocessor system which shares a main storage has a execution circuit for executing a compare and watch instruction provided for watching information for synchronization written into a main storage. When one program being executed by one of the processors issues an instruction, the circuit fetches information for synchronization from a location within the main storage designated by the instruction, compares that fetched information with another information designated by the instruction. If they do not have a specific relation, the fetching and the comparison is repeated. The circuit has a circuit for limiting the repetition with a limited number of times. The circuit further has a circuit for counting a total amount of CPU time spent for execution of plural watching instructions issued by the same program.

Information processing system capable of executing a single instruction

An arrangement having a register file having registers greater in number than those which are designated by an instruction, a pipeline ALU, a current window pointer and window number modifier operating in a register window mode, an element counter and address counter operating in a vector register mode, and register determining circuits for determining physical register numbers from the register numbers designated by an instruction in one of the two modes. Each register determining circuit has a first register determining circuit using an output of the window number modifier, for using the register file as a register window configuration, and a second register determining circuit using an output of the element counter, for using the register file as a vector register configuration. Physical registers of the register file are used as scalar registers in the register window mode, and used as vector registers in the vector register modes.

Information processing apparatus having a register file used

A data processor having memory requesters to execute instructions, an instruction hold unit disposed for each resource to hold an instruction being executed in the resource and instructions to be executed therein, and execution control units to cause, in a case where an execution completion report of an instruction being executed in either one of the resources is received, an instruction held in an instruction hold unit corresponding to the resource to be immediately executed, thereby successively supplying the respective resources with data items to be employed for executions of the consecutive instructions in the resources.

Data processor having resources and execution start control for starting

A plurality of storage control units are employed in the storage control unit section; moreover, two requester modules are adopted in association with these storage control units. Each memory module is constituted with as many access bank groups as there are storage control units. The access bank groups operate in concurrent fashion and are accessible from any one of the storage control units. In the element assignment, a plurality of request control units in each requester module and a plurality of vector data controllers in each vector register unit are respectively assigned with serial numbers beginning from zero. For a vector data controller, a number assigned thereto is divided by the request module count to attain a remainder such that the vector data controller is assigned to a request module having a number identical to the value of the remainder. Furthermore, a request queue is disposed at a stage preceding each priority unit and a request send-out unit is arranged to store therein a state of the request queue and to control a request transmission from each request control unit. Addresses are assigned to the respective memory modules, bank groups, and banks according to skew schemes respectively suitable therefor.

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Kodaira, Japan

Yoshiko Tamaki