Kabushiki Kaisha Toshiba

Yoshiki Tsukiboshi

Takeshi Kitahara

A clock design apparatus includes a delay time adjusting section, a prohibition specifying section and a clock tree synthesis section. The delay time adjusting section is configured to adjust signal delay time of signal propagation paths on a semiconductor integrated circuit to be designed. The prohibition specifying section is configured to specify a part of the signal propagation paths as a circuit prevented from being changed. The clock tree synthesis section is configured to synthesize a clock tree of the semiconductor integrated circuit in accordance with the specification made by the prohibition specifying section.

Clock design apparatus and clock design method

In a placing design employing standard cell system, a series of steps of merging, improving arraying in one-dimensional array and division are fundamentally alternately repeated to obtain a two-dimensional array of a plurality of cells which have relations interconnections. In the automatic cell placing method, since division is always performed after merging, placing obtained in the previous step can be corrected resulting in placing design having small dispersion in wiring density distribution.

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Tokyo, Japan

Yoshiki Tsukiboshi