Fujitsu Corporation

Yoshiki Shimauchi

Hiromu Enomoto

Yasushi Yasuda

Akinori Tahara

Shinzou Satou

Katsuji Hirochi

A semiconductor integrated circuit has an output circuit which includes a Bi-CMOS circuit of receiving an input signal, and an ECL circuit. The ECL circuit includes a differential pair for receiving an output of the Bi-CMOS circuit, na an emitter follower for receiving an output of the differentail pair. The Bi-CMOS circuit comprises a CMOS inverter connected in series between power sources; a first npn transistor, a diode, and a second npn transistor which are connected in series between the power sources; and second and third n-channel MOS transistors for turning the second npn transistor ON and OFF. This semiconductor integrated circuit provides a stable, operation and low power consumption.

Integrated semiconductor circuit

Electrostatical breakage of a semiconductor device, including an epitaxial layer and a buried layer thereunder, connected to an outer signal terminal, can be prevented by forming an impurity region in the epitaxial layer so as to form a PN junction between the buried layer and the impurity region. The impurity region is connected to a power source or ground.

Semiconductor device with PN junction isolation for TTL or ECL circuits

A gate array LSI device having inner gate circuits whose performance is not affected by the load condition and having a large fan-out number. The inner gate circuit comprises one or more PNP-type transistors, each of which receives an input signal at the base thereof, a first NPN-type transistor whose base is connected to the emitters of the PNP-type transistors, and an output buffer circuit. The output buffer circuit includes a second NPN-type transistor, which is controlled by the signal at the emitter of the first NPN-type transistor and outputs electric charges from an output terminal, and a third NPN-type transistor, which is controlled by the signal at the collector of the first NPN-type transistor and which is connected in series with the second NPN-type transistor so as to supply a charging current to the output terminal.

Gate array LSI device using PNP input transistors to increase the

A level shift element is connected between a transistor (Tr.sub.5) which is used to determine a threshold level when the input voltage falls and a diode (D.sub.3) is connected between an input terminal and an output control transistor (Tr.sub.2) to discharge the base of the output control transistor. The level shift element comprises a diode connected in the forward direction or a resistor.

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Kawasaki, Japan

Yoshiki Shimauchi