Sharp Kabushiki Kaisha Corporation

Yoshiki Sano

Junji Tanaka

Yoshinori Ogawa

Yukihisa Orisaka

Masakazu Kobayashi

Masahiko Monomohshi

Kiyohisa Matsui

Hiroyuki Hirashima

Tatsuya Nakai

A liquid crystal display panel 51 of N rows.times.M columns is driven by a segment driver 52 with two different voltages VS1, VS2, and by a common driver 53 with three voltages VC1, VC2, VC3. An output voltage waveform of the segment driver 52 is modulated for gradation display. The two different voltages VS1, VS2 are selected to be low voltages so as not to require high withstand voltage process in the segment driver 52, which makes it easier to integrated to a large scale in the case of realizing the segment driver 52 as a semiconductor integrated circuit.

Liquid crystal driving device

A liquid crystal driver circuit is arranged to select one of a plurality of different reference voltages in response to externally input through the effect of a multiplexer circuit. The liquid crystal driver further provides a buffer circuit at an output stage of the multiplexer circuit, arranged in a manner that its impedance is high at an input and low at an output to thereby lower an output impedance of the liquid crystal driver circuit.

Liquid crystal driver circuit

A sample/hold apparatus includes at least one sample/hold circuit. The at least one sample/hold circuit has a resistor connected to an input bus at one end thereof, a sampling gate connected to the other end of the resistor at one end thereof for opening and closing in response to a sampling signal supplied thereto, and a first capacitor connected to the other end of the sampling gate at one end thereof for holding analog data supplied from the input bus through the resistor and the sampling gate.

Apparatus for sampling and holding analog data for a liquid crystal

A sample-and-hold circuit includes two capacitors connected to an input signal line through respective analog switches for holding an input signal. An amplifier circuit of the sample-and-hold circuit includes two input terminals for receiving voltages held in the respective two capacitors and for amplifying the received voltages. The amplifier circuit alternately amplifies the voltages received through the two input terminals.

Sample-and-hold circuit

An output circuit having a buffer, the buffer including the first transistor which receives at a gate thereof a periodic input voltage and the second transistor, the first and the second transistors being connected in series across a power line and a ground line, a junction of the first and second transistors being connected to an output terminal. The output circuit includes a circuit for applying, to a gate of the second transistor, a first voltage for the second transistor to serve as a bias transistor for charging a load connected to the output terminal with a voltage corresponding to the input voltage, and the second voltage greater than the first voltage for the second transistor to serve as a discharge transistor for discharging the load.

Output circuit with buffer

A capacitor having a semiconductor substrate with a diffusion layer disposed in a portion of the semiconductor substrate and a first insulation layer disposed on the semiconductor substrate and the diffusion layer, the capacitor capable of providing a capacitance stably for an integrated circuit includes a first metallic layer disposed on the diffusion layer for conducting an electric current therethrough with the first insulation layer between the semiconductor substrate, a second insulation layer disposed on the first metallic layer for insulating the first metallic layer, and a second metallic layer disposed on the second insulation layer for conducting an electric current therethrough, the capacitance being expressed by C with a relation of C=C.sub.M +C.sub.B, the C.sub.M representing a capacitance occurred between the first metallic layer and the second metallic layer, the C.sub.B representing a capacitance occurred between the first metallic layer and the semiconductor substrate, respectively. The capacitor includes a third metallic layer which is disposed on the diffusion layer for conducting an electric current therethrough, and a third insulation layer which is disposed on the second metallic layer for protecting the integrated circuit. The capacitor also includes a mold resin which is disposed on the third insulation layer for sealing the capacitor.

Growing community of inventors

Kashihara, Japan

Yoshiki Sano