Oki Electric Industry Co., Ltd.

Mitsubishi Denki Kabushiki Kaisha

Lapis Semiconductor Co., Ltd.

Envision Aesc Japan Ltd.

Yoshiki Kobayashi

Toru Suzuki

Akira Sakata

Takayuki Itou

A battery pack houses a battery inside a battery case, the battery case () includes an opening (), cables () electrically connected with the battery is inserted to the opening, a cable protection member () including a through portion () is arranged at the opening, the cable protection member is attachable to the opening in at least two different directions, and a position of the through portion to the battery case changes according to an attaching direction.

Battery pack

Disclosed is a semiconductor integrated circuit capable of efficiently performing debugging. The semiconductor integrated circuit includes a distributing part distributing received packets according to destinations of the packets, a plurality of accumulating parts sequentially accumulating the packets distributed thereto, respectively, a plurality of relaying parts supplying the packets accumulated in one of the accumulating parts to corresponding one of the processing parts, respectively, and an output controlling part assigning the relay permission command to one relaying part designated by a relay permission packet from among the relaying parts when a packet distributed thereto from the distributing part is determined as the relay permission packet.

Semiconductor integrated circuit

The number of S-FFs in a scan-path is decreased by half and a test time needed is decreased. An I/O terminalA is connected to a scan-path-and a combination circuitvia a selectorA and an output of the scan-path-is connected to an I/O terminalB via a selectorA and a tri-state bufferA. The I/O terminalB is connected to a scan-path-and to the combination circuitvia a selectorB and the output of the scan-path-is connected to the I/O terminalA via a selectorB and tri-state bufferB. When testing, the tri-state buffers are turned off and test-data are supplied by connecting the I/O terminalA,B to the scan-path--respectively. Thereafter, output signals of the combination circuit is applied to each S-FFand the test data are read out from the I/O terminalA,B by turning on the each tri-state bufferA,B.

In a semiconductor memory device according to the present invention, which allows a memory cell array unit and a memory circuit internal logic unit to be tested independently of each other, a first test circuit unit TCi to which an address signal a&Prime;, a scan-in signal SIN, a scan select signal SS and a shift clock signal SCLK are input, outputs an address signal a&prime;&Prime; and a scan-out signal SiOUT The address signal a&prime;&Prime; is input to the memory cell array unit MCA and a column selector CS, whereas the scan-out signal SiOUT is input to a second test circuit unit TCi The second test circuit unit TCi to which the scan-out signal SiOUT the scan select signal SS, a write control signal WCTRL and a scan clock signal SCLK are input, outputs at a scan-out signal SOUT. The first test circuit unit and the second test circuit unit each achieve a parallel/serial conversion function.

Semiconductor memory device

An oil control valve includes a cylindrical valve housing and ports and formed in a periphery of the valve housing so as to face pipes, respectively, that guide hydraulic oil to an actuator. The valve housing is provided with a groove that provides communication between the port and the pipeline and a groove that provides communication between the port and the pipeline.

Growing community of inventors

Kanagawa, Japan

Yoshiki Kobayashi