Kabushiki Kaisha Toshiba

Kioxia Corporation

Toshiba Memory Corporation

Yoshiki Kamata

Yoshiaki Asao

Misako Morota

Yukihiro Nomura

Daisaburo Takashima

Takahiko Iizuka

Ryu Ogiwara

Iwao Kunishima

Rieko Funatsuki

Kazuhiko Yamamoto

Akira Nishiyama

Akira Takashima

Tsutomu Tezuka

Hidehiro Shiga

Yoshihiko Moriyama

Yuki Ito

Bairu Yan

Shigeru Kawanaka

A variable resistance non-volatile memory includes a memory cell including a core portion extending in a first direction above a semiconductor substrate, a variable resistance layer extending in a first direction and in contact with the core portion, a semiconductor layer extending in a first direction and in contact with the variable resistance layer, an insulator layer extending in a first direction and in contact with the semiconductor layer, and a first voltage application electrode extending in a second direction crossing the first direction and in contact with the insulator layer. An impurity concentration of the semiconductor layer is non-uniform, such that an impurity concentration of a first portion of the semiconductor layer in contact with the insulator layer is at least ten times higher than an impurity concentration of a second portion of the semiconductor layer in contact with the variable resistance layer.

Variable resistance non-volatile memory

A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.

Memory device and method of manufacturing memory device

According to one embodiment, a memory device includes a first electrode, a second electrode, and a resistive layer provided between the first electrode and the second electrode, containing at least one of antimony (Sb) and bismuth (Bi) as a first element, and tellurium (Te) as a second element, and having a variable resistance value. The resistive layer includes a first layer having a hexagonal crystal structure containing the first element and the second element. The first layer contains a group 14 element as a third element.

Memory device

A semiconductor memory device, includes: a stack including a wiring layer and an insulation layer alternately stacked in a first direction; a semiconductor layer including a first region overlapping with the insulation layer in a second direction, and a second region overlapping with the wiring layer in the second direction; an insulation region between the wiring layer and the second region; and a memory region on the opposite side of the second region from the wiring layer. The wiring layer is farther from the first region in the second direction than the insulation layer is. The second region has a part between the insulation layers in the first direction and protruding further toward the wiring layer than the first region in the second direction. The memory region has a face opposite to the second region and closer to the wiring layer in the second direction than the first region is.

Semiconductor memory device having memory layer extending between insulation layer and semiconductor layer

According to one embodiment, a memory device includes a stacked structure including a plurality of conductive layers stacked to be apart from each other in a first direction, and a pillar structure including a resistance change portion extending in the first direction in the stacked structure, and a semiconductor portion which extends in the first direction in the stacked structure and which includes a first portion provided along the resistance change portion and a second portion extending from the first portion in at least one direction intersecting the first direction.

According to one embodiment, a nonvolatile memory device includes a first conductive portion, an insulating film surrounding a side surface of the first conductive portion, an intermediate layer provided on the first conductive portion and the insulating film, a first film including a first portion provided on the intermediate layer and at least one second portion provided in the intermediate layer and outside an upper edge of the first conductive portion, the first film including, above the first conductive portion, a resistance change portion that has a first resistance state and a second resistance state having resistance higher than resistance in the first resistance state, and a second conductive portion provided at least on the resistance change portion.

Nonvolatile memory device and method of manufacturing the same

According to one embodiment, a superlattice memory comprises substrate, a first electrode provided on the substrate, a second electrode arranged in opposition to the first electrode, and a superlattice structure part provided between the first electrode and the second electrode, which includes first chalcogen compound layers, second chalcogen compound layers the composition of which is different from the first chalcogen compound, and contains Ge, and third chalcogen compound layers in which one of N, B, C, O, and F is added to the first chalcogen compound, stacked one on another.

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According to one embodiment, a memory device includes a nonvolatile memory element including a stacked structure and having a first resistive state and a second resistive state having higher resistance than the first resistive state, the stacked structure including a first layer containing bismuth (Bi) and tellurium (Te) and a second layer containing germanium (Ge) and tellurium (Te).

A memory device according to an embodiment includes a first conductive layer, a second conductive layer, a third conductive layer intersecting the first conductive layer and the second conductive layer, and a resistance change layer including a first region which is provided between the first conductive layer and the third conductive layer and has a superlattice structure, a second region which is provided between the second conductive layer and the third conductive layer and has the superlattice structure, and a third region which is provided between the first region and the second region. The third region includes at least one element selected from the group consisting of O, F, C, P, B, N, H, Bi, Cd, Zn, Ga, Se, Al, S, Be, In, and Pb. Concentration of the at least one element in the third region is higher than that in the first region and the second region.

According to one embodiment, a memory includes a resistance change layer includes a first chalcogenide layer, and a second chalcogenide layer having a composition different from that of the first chalcogenide layer which are stacked alternately, and the resistance change layer having a superlattice structure, and a semiconductor layer of a first conductivity type provided on a one of main surfaces of the resistance change layer.

Superlattice memory and crosspoint memory device

According to one embodiment, a memory device includes a superlattice structure portion containing first chalcogen-compound layers and second chalcogen-compound layers differing in composition from the first chalcogen-compound layers are alternately deposited, a first layer provided on one of main surfaces of the superlattice structure portion in a deposition direction thereof, which has a larger energy gap than that of the superlattice structure portion, and a second layer provided on the other main surface of the superlattice structure portion in the deposition direction, which has a larger energy gap than that of the superlattice structure portion.

According to one embodiment, a field-effect transistor includes a source region of a first conductivity type, a drain region of the first conductivity type and a channel region of the first conductivity type between the source region and the drain region, the source region, the drain region and the channel region being disposed in a polycrystalline semiconductor layer; a first layer including an amorphous semiconductor layer disposed on the channel region; a gate insulating layer disposed on the first layer; and a gate electrode disposed on the gate insulating layer.

Field-effect transistor and semiconductor device

An exemplary embodiment provides a semiconductor device, in which a junction leakage current is reduced in MISFET including a source/drain impurity layer formed in a semiconductor region containing Ge, and a semiconductor device manufacturing method. The semiconductor device includes a channel region which is formed in a semiconductor substrate; a gate insulator which is formed on a surface of the channel region; a gate electrode which is formed on the gate insulator; and source/drain impurity layers which are formed on both sides of the channel region. In the semiconductor device, at least part of the source/drain impurity layer is formed in a semiconductor region containing Ge in the semiconductor substrate, and at least an element selected from a group including S, Se, and Te is contained in the semiconductor region which is deeper than a junction depth of the source/drain impurity layer.

Semiconductor device and manufacturing method thereof

A semiconductor device includes an NMISFET region. The NMISFET region includes a Ge nano wire having a triangular cross section along a direction perpendicular to a channel current direction, wherein two of surfaces that define the triangular cross section of the Ge nano wire are (111) planes, and the other surface that define the triangular cross section of the Ge nano wire is a (100) plane; and an Si layer or an SiGelayer (0&#x3c;x&#x3c;0.5) on the (100) plane of the Ge nano wire.

Growing community of inventors

Tokyo, Japan

Yoshiki Kamata