Nippon Telegraph and Telephone Corporation

Ntt Electronics Corporation

Ntt Innovative Devices Corporation

Ntt Corporation

Nippon Telephone and Telegraph Corporation

Yoshikazu Urabe

Masatoshi Tobayashi

Tadashi Minotani

Toshiki Kishi

Masahiro Endo

Masafumi Nogawa

Hatsushi Iizuka

Makoto Nakamura

Hiroshi Koizumi

Kazutaka Hara

Hirotaka Nakamura

Shunji Kimura

Shinsuke Nakano

Yuhki Imai

Koji Kitahara

Yohtaro Umeda

Kazuyoshi Nishimura

Jun Endou

Yuji Akatsu

Hiroaki Sanjoh

Yuuki Imai

Eiji Hyodo

Nobuhiro Toyoda

The transmission interface includes a plurality of transmitters, wherein the transmitters are provided with: a power supply terminal shared by the plurality of transmitters, configured to receive a ground voltage; a bias terminal configured to receive a bias voltage; signal terminals configured to receive a signal voltage; a power supply fluctuation inverting bias unit to which a ground voltage and a bias voltage are applied, and which outputs the ground voltage making its fluctuation 180 degrees out of phase; a modulation unit to which the output of the power supply fluctuation inverting bias unit and a signal voltage are applied, and which outputs the opposite phase ground voltage making its fluctuation in phase; and a laser diode to which the ground voltage and the output of the modulation unit are applied.

Transmission interface and transmitter

An embodiment is a connecting circuit connected to the preceding stage of a transmission circuit and configured to receive a baseband signal, includes an isolation element connected between an input terminal and an output terminal, a signal midpoint detection circuit connected parallel to the isolation element, a bias adding circuit connected in series with the signal midpoint detection circuit, and an initial voltage value detection circuit connected to a frame detection circuit. The initial voltage value detection circuit holds an initial voltage value of the baseband signal in accordance with the signal of the frame detection circuit, and outputs the initial voltage value to the signal midpoint detection circuit. The signal midpoint detection circuit detects a midpoint voltage from the baseband signal and the initial voltage value, and outputs the midpoint voltage to the bias adding circuit. The bias adding circuit adds the midpoint voltage to a bias voltage.

Connecting circuit and communication interface

An amplifier circuit includes: an amplifier connected to an isolating element; a signal midpoint detecting circuit connected in parallel with the isolating element; a bias adding circuit connected in series with the signal midpoint detecting circuit; and an initial voltage value detecting circuit connected to the frame detecting circuit. The initial voltage value detecting circuit holds an initial voltage value of the baseband signal using a signal from the frame detecting circuit, and outputs the initial voltage value to the signal midpoint detecting circuit. The signal midpoint detecting circuit detects a midpoint voltage from the baseband signal and the initial voltage value, and outputs the midpoint voltage to the bias adding circuit. The bias adding circuit adds the midpoint voltage to a bias voltage for biasing the baseband signal. The amplifier amplifies the baseband signal.

Amplifier circuit

An amplifier typically exemplified by a TIA is realized that provides an optimal band characteristic, that reduces the possibility of the oscillation, and that achieves a reduced dispersion of the band characteristics. An amplifier for amplifying an electric signal, comprising: a first buffer for amplifying the electric signal; a filter that is connected to an output of the first buffer and that includes a parallel circuit consisting of an inductor and a first capacity; and a second buffer connected to an output of the filter.

Amplifier

A comparator () outputs, out of an electrical signal input from a trans impedance amplifier (TIA) via a coupling capacitor, pulses having amplitudes equal to or larger than a reference value as a comparison output signal (Cout). An analog holding circuit () charges a holding capacitor with each pulse contained in the comparison output signal (Cout) and also removes a DC voltage obtained by the charging via a discharging resistor, thereby generating a holding output signal (Hout) that changes in accordance with the presence/absence of input of an optical signal. This allows to perform an autonomous operation without any necessity of an external control signal and properly detect the presence/absence of input of an optical signal.

Optical signal cutoff detection circuit and optical receiver

In the present invention, unlike a conventional circuit, discrimination is not made by integrating a logical code that includes '0' and '1' to some extent and produced from a random code, but repetition of an identical pattern of a well-known preamble signal added to a head portion of a signal is discriminated when a bit-rate of the signal is changed. More specifically, the repetition of the identical pattern is converted into a consecutive identical signal to generate the consecutive identical signal (having a length of tens bits to thousands bits). Although the consecutive identical signal is longer than a same-code continuation length included in the signal, and is shorter than a time constant necessary to the conventional circuit by about one to three digits. Therefore, an integration time can be shortened to the same degree as the generated consecutive identical signal length, and the bit-rate can be discriminated at high speed within a preamble signal receiving time.

Bit-rate discrimination method and its apparatus

A receiving method according to the present invention adjusts a level of an output voltage signal by switching a gain to be used for converting an inputted current signal to a voltage signal, in a preamplifier. Performing offset compensation on the output voltage signal in an offset compensator, in a post amplifier. Adding a reset signal, whose polarity is made opposite to a polarity of the output voltage signal, to the output voltage signal, in the preamplifier. Detecting the reset signal having added to the output voltage signal, and resetting the offset compensator by use of the detected reset signal, in the post amplifier.

Receiving method and receiving circuit

A gain switching determination circuit () compares/determines a comparative input voltage (Vc) from an inter-stage buffer () with a first hysteresis characteristic, and outputs a gain switching signal (SEL) based on the comparison/determination result to first and second transimpedance amplifier core circuits (), thereby switching the gains of the core circuits. This obviates holding a comparison input voltage with long response time in a level holding circuit for gain switching determination, which allows instantaneous gain switching determination and instantaneous response corresponding to burst data.

Transimpedance amplifier

Growing community of inventors

Ebina, Japan

Yoshikazu Urabe