Hitachi, Ltd.

Hewlett-Packard Company

Yoshikazu Tanaka

Kyoko Iwasawa

Yoshiko Tamaki

Yuji Tsushima

Yasuhiro Inagami

Katsuyoshi Kitai

Shizuo Gotou

Kentaro Shimada

Rajiv Gupta

Shunichi Torii

Shigeo Nagashima

Naohiko Irie

Kyugo Hamai

Hideki Sekiguchi

Yooichi Shintani

Yonetaro Totsuka

Frederic C Amerson

William S Worley, Jr

B Ramakrishna Rau

Masanao Ito

Shogo Miyamoto

Eiji Nunohiro

Kazuhiro Aida

The invention provides a power transmission apparatus for vehicle which can realize a high torque transmission efficiency and a high reduction gear ratio of a reduction gear unit with a more compact structure, and a vehicle-driving electric machinery system using the power transmission apparatus for vehicle. The power transmission apparatus for vehicle comprises a motor, a reduction gear unit for decelerating power outputted from the motor, and a differential gear unit for distributing the power decelerated by the reduction gear unit to left and right wheels. The reduction gear unit is a reduction gear mechanism including a plurality of gears mounted over a shaft which is rotatably held by a housing in a fixed position. The reduction gear unit and the differential gear unit are arranged within an area in oppositely facing relation to an axial end surface of the motor.

Power transmission apparatus for vehicle and vehicle-driving electric machinery system using the same

Each small instruction in a VLIW instruction (long instruction) is added with the number of NOP instructions which succeed the small instruction, and these NOP instructions are deleted from the succeeding long instruction. A plurality of long instructions are therefore time-compressed. Thereafter, a plurality of small instructions in each long instruction are divided into a plurality of groups, and a combination of operation codes (OP codes) of small instructions in each group is replaced by a group code to generate a compressed, grouped instruction. Each long instruction is therefore space-compressed. An instruction expanding unit has an instruction expanding circuit for each grouped instruction. Each instruction expanding circuit expands one grouped instruction in a long instruction, generates a group of small instructions represented by the grouped instruction, and supplies the group of generated small instructions to respective function units via a decode unit. In this case, each instruction expanding circuit supplies after each small instruction NOP instructions same in number as that designated by a NOP number associated with each small instruction in this grouped instruction.

Processor for VLIW instruction

A method and apparatus for handling a large-capacity register file by using a small instruction field as to support a software pipeline. The invention includes a register file having a plurality of physical registers corresponding to a plurality of physical register numbers and a converter which converts logical register numbers included in instructions to be executed into physical register numbers. A physical register, which is used when a logical register is accessed as a result of execution of an instruction, is specified by a pointer corresponding to the logical register number included in the instruction. The pointer used for the access is incremented if so specified in the instruction to ensure that subsequent instructions making access to the same logical register use different physical registers.

Processor having a register configuration suited for parallel execution

To improve the function of a circuit for prefetching data accessed by a processor, a prefetch unit incorporates therein a circuit for issuing a request to read out one group of data to be prefetched and registers for holding the group of data read in response to the read request therein. The group of data are read out from a cache memory or a main memory under the control of a cache request unit. A plurality of groups of data can be prefetched. When data designation is made, the processor requests the cache memory to read a block to which the data to be prefetched belongs. A circuit is also included in the prefetch unit, wherein when prefetched data is subsequently updated by the processor, its updated data is made invalid. Elements of a vector complex in structure, such as an indexed vector or the like can be also read out. It is also possible to cope with an interrupt generated within the processor.

Information processing apparatus with prefetch control for prefetching

The system for executing processes in parallel in a multiprocessor system having plural instruction processors performs parallel processing by converting a source program written in a high-level language into an object module, creating parallel processes for the processing of the parallel-executable parallelling object segment, and executing the parallel processes on the plural instruction processors. In the object module, a run cost value is set for giving a standard of a run time for the parallel-executable parallelling object segment, and the number of the parallel processes to be created is determined in accordance with the run cost value immediately prior to the execution of the parallel processes. Then, the parallel processes are created in the number determined to be created, and the parallel processing is performed by the execution of the parallel processes.

System and method for determining the number of parallel processes to be

Each processor of a multiprocessor system which shares a main storage has a execution circuit for executing a compare and watch instruction provided for watching information for synchronization written into a main storage. When one program being executed by one of the processors issues an instruction, the circuit fetches information for synchronization from a location within the main storage designated by the instruction, compares that fetched information with another information designated by the instruction. If they do not have a specific relation, the fetching and the comparison is repeated. The circuit has a circuit for limiting the repetition with a limited number of times. The circuit further has a circuit for counting a total amount of CPU time spent for execution of plural watching instructions issued by the same program.

Information processing system capable of executing a single instruction

In a method of generating an object program for a multiprocessor system from a source program including a loop, there is detected a variable in the loop. For the detected variable, first codes providing a one-dimensional work array are added to the source program. The work array has elements whose the number is predetermined according to a maximum number of parallel processes to be generated for the loop and is shared among the parallel processes. It is determined whether or not the variable is used outside the loop. When it is determined that the variable is not used at any position outside the loop, the source program with the first codes added is compiled to produce the object program, thereby executing the loop in a parallel fashion by the parallel processes using the elements of the work array as a local variable associated with the variable.

Method of generating from source program object program by which final

In a parallel computer, a method for controlling a debugging process includes the steps of registering identifiers of plural processors into an execution waiting queue in a predetermined order; executing a corresponding program by each of the processors in an order until it is brought into either a waiting state or an end state; registering the identifier of the processor of the waiting state as a last element of the execution waiting queue; and repeating the executing step until there are no executable processors. A program having a bug is determined from the identifiers left in the execution waiting queue. Further, the debugging-process control method further includes outputting trace data during execution of the executing step, the program having the bug is determined from this trace data.

Method for debugging in a parallel computer system and system for the

In a processor system for executing a plurality of tasks, which respectively control execution of one or more of a plurality of processes, a method of restarting execution of a first process which is under control of a specific task being executed, after the first process is stopped to wait for occurrence of an event associated with at least one second process different from the first process, includes the steps of (a) detecting whether or not the event associated with the second process has occurred; (b) restarting the execution of the first process when it is detected that the event has occurred; (c) determining whether or not there is an execution waiting process when the event has not yet occurred; (d) executing an executing waiting process when there is any; and (e) repeating the steps (a) to (d) after execution of an execution waiting process when there is any or after the step (c) when there is not such an execution waiting process.

Processor system for executing processes in parallel under multitask,

In order to make parallel processing of a serial execution type user program automatically and at a high speed without re-coding, an object code is parallelized by detection of the possibility of parallel execution in an iteration unit of a loop, detection of the possibility of parallel execution of each statement in the loop, the interchange of an outer loop by an inner loop of a multiple loop, reduction of the multiple loop to a single loop, inclined coversion for making parallel execution along a wave front plane (line) when sufficient multiplicity is not derived, and the program which is estimated to have the shortest processing time is selected from the granularity, and multiplicity of the object code, the variance of the number of instructions and the proportion of synchronization control at the time of parallelization of the object code.

Parallelization compile method and system

In a compiling method, whether a variable (induction variable)recurrsively defined during loop iteration is included in an iteratively executed loop portion of a source program is detected. If such a variable is detected, a computation program portion for calculating a value of the variable which the variable should have during loop iteration of an arbitrary loop iteration number is generated. A plurality of parallely executable object program portions each for executing one of a plurality of processing to be executed during loop iteration of a respective loop iteration number of the loop portion is generated. Each of the object program portions includes a portion for executing the generated computation program portion for a respective loop iteration number to calculate a value of the variable for that loop iteration number.

Method for converting an iterative loop of a source program into

A compiling method is provided for vectorizing outer sides of multiple loops which are not tight. The method detects variables which are defined in one loop and referenced by another. The information, mapped into a dependence graph, is used to analyze the data dependency of each loop level and expand the source program. The value of the variable is substituted for an appropriate element of the array and the value of the appropriate element of the array is substituted for an original variable. The compiler inserts control statements to assure initial values and end values for the loops are preserved minimizing the size of the working arrays, and vectorizing multiple loops for each loop level.

Compiling method for vectorizing multiple do-loops in source program

Vectorization is enabled in a source program having a conditional branch in a loop in which a sequence of definition and reference of data is disordered by the vectorization. A statement reordering part having a conditional statement moving part, and a loop splitting part are provided in an automatic vectorization processing part of a compiler. The statement reordering part reorders the statements by moving the statements in the source grogram to any desired position so that the sequence of definition and reference of data is converted to the vector instructions. If the statement to be moved is a conditional one, the associated condition statement is also copied and moved together with it. The loop splitting part splits the source program loop into a vector loop and a scaler loop when the loop in the source program contains both statements which can be vectorized and statements which can not be vectorized. If a split point is under a condition statement, the condition statement is copied into the scaler loop and the vector loop. As a result, the execution condition for the statements does not change before and after the loop split. In this manner, the portion which can not be vectorized is minimized for the loop which contains the conditional branch.

Method for converting a source program of high level language statement

An array processor includes a central vector processing unit including a plurality of vector registers and a pipe-line control arithmetic and logical operation unit (ALU) operative to execute an instruction (vector instruction) requiring vector processing, and a plurality of vector processing units including a plurality of vector registers and a pipe-line control ALU operative to execute an instruction (array instruction) requiring array processing. The central vector processing unit fetches and decodes the vector instruction or the array instruction to execute the decoded instruction, when this instruction is a vector instruction, but operates to start the vector processing units when the decoded instruction is an array instruction. Each of the vector processing units executes that operation to one of plural vector data comprising array data to be an object of the operation designated by the decoded instruction, which is designated by the instruction for one of the vector data, when the decoded instruction is an array instruction. When the result of the operation designated by the array instruction is vector data, each of the vector processing units computes and stores one element of vector data in built-in scalar registers, and sends out that element to the central vector processing unit so that the element may be stored in vector registers in the central vector processing unit. When the result of the operation designated by the array instruction is array data, each of the vector processing units computes and stores one vector data of those resultant array data in built-in vector registers.

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Omiya, Japan

Yoshikazu Tanaka