Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Yoshikazu Takeyama

Masaru Koyanagi

Yuji Nagai

Akio Sugahara

Mitsuaki Honma

Jun Nakai

Noboru Shibata

Toshihiro Suzuki

Atsushi Inoue

Hiroshi Sukegawa

Katsuaki Isobe

Jumpei Sato

Mikio Ogawa

Takayuki Harima

Koichi Shinohara

Yuujiro Shimada

Keizo Mori

A memory system includes a semiconductor storage device and a memory controller for the semiconductor storage device. The semiconductor storage device includes a plurality of blocks including a plurality of memory cell transistors. The plurality of blocks includes a first block and a second block. The memory cell transistor in the first block stores data having a first number of bits during a first period and stores data having a second number of bits larger than the first number during a second period that begins after the first period ends.

Memory system

According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal.

Semiconductor storage device and control method thereof

According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit information and is a comparison target of a chip address, and is used for identifying its own memory chip, a second storage unit that stores therein second information for determining an effective bit of the n-bit first information, and a control unit that determines an effective bit of the n-bit first information and an effective bit of the chip address based on the second information.

Memory system and assembling method of memory system

According to one embodiment, a semiconductor memory device includes a memory cell array, a first circuit, and a second circuit. The first circuit executes program and read. The program is processing for changing a threshold voltage of a memory cell to a voltage according to data. The data includes first data of a bit and second data of a bit. The program of the second data is executed after the program of the first data. The read includes measuring the threshold voltage. The second circuit manipulates a flag in accordance with execution of the program of the second data. In a case where the second data is a target of the read, the second circuit refers to the flag. In a case where the flag indicates non-execution of the program of the second data, the second circuit aborts the measuring before the measuring of the threshold voltage is completed.

Semiconductor memory device, control method, and memory system

According to one embodiment, a semiconductor memory device includes a memory cell array including a plurality of memory cells, a random number generation circuit configured to generate a random number, and a controller configured to control the memory cell array and the random number generation circuit. The random number generation circuit includes a random number control circuit configured to generate a random number parameter based on data which is read out from the memory cell by a generated control parameter, and a pseudo-random number generation circuit configured to generate the random number by using the random number parameter as a seed value.

Semiconductor memory device for pseudo-random number generation

A memory system includes nonvolatile memory having a plurality of memory cells of storage capacity of a specified number of bits equal to or greater than two bits, and a number-of-rewrites management table managing numbers of rewrites of the memory cells. The memory system includes a controller writing to the memory cells in a number of bits in accordance with a write request of a host, dividing the memory cells into groups in dependence on storage capacity after the numbers of rewrites of the memory cells managed by the number-of-rewrites management table exceed a specified number, and writing to the memory cells of the group corresponding to storage capacity of the number of bits in accordance with the write request of the host.

Memory system, controller, and method for controlling memory system

According to one embodiment, a memory system includes a NAND flash memory includes a memory cell array includes pages, and a volatile data register with a storage capacity of one page, and configured to write page data to the memory cell array through the data register, each of the pages includes nonvolatile memory cells and being a unit of data write, a volatile RAM, and a controller includes a power saving mode in which power consumption of the RAM is reduced, and configured to transfer data of the RAM to the data register before entering the power saving mode.

Memory system and server system

A memory cell array includes a plurality of memory cells in each of which a plurality of bits are stored. A sense amplifier detects data read from a memory cell selected from the memory cell array. At the time of a write verify operation for verifying write data, when a threshold voltage of the memory cell exceeds a predetermined checkpoint, the data control unit converts write data to be written to the memory cell into data of the number of times indicating the remaining number of write voltage application times, inverts only one bit of the data of the number of times each time a write voltage application operation is performed, and changes a definition of the data of the number of times to thereby perform a subtraction operation.

Nonvolatile semiconductor storage device capable of high-speed writing

A write controller performs verification for checking whether each memory cell is on a predetermined verification level. For a memory cell to be written to a voltage level higher than the predetermined verification level, the write controller stores, in first and second latch circuits, the number of times of write to be performed by a write voltage after the verification. Whenever write is performed by the write voltage, the write controller updates the number of times of write stored in the first and second latch circuits. After write is performed the number of times of write by the write voltage, the write controller performs write by an intermediate voltage lower than the write voltage.

Nonvolatile semiconductor memory including memory cell for storing multilevel data having two or more values

A power supply circuit outputs different set potentials in response to control signals, wherein a voltage detecting circuit changes levels of a first reference potential and a second reference potential in response to inputs of control signals, and a clock generating circuit increases a frequency of the frequency divided clock signal when the levels of the first reference potential and the second reference potential are greatly changed in response to the inputs of the control signals.

Growing community of inventors

Fujisawa, Japan

Yoshikazu Takeyama