Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Yoshikazu Saito

Kiyoo Itoh

Takao Watanabe

Yutaka Kobayashi

Ryoichi Hori

Goro Kitsukawa

Katsuhiro Shimohigashi

Takahide Ikeda

Noriyuki Homma

Hideaki Uchida

Shinji Nakazato

Masahiro Yamamura

Nobuo Tanba

Kenichi Osada

Takayuki Kawahara

Ken Yamaguchi

Naoki Kitai

Akira Ide

Yoshiaki Yazawa

A semiconductor device includes a plurality of memory cells, and an error-correction circuit. Its write operation is performed by a late-write method, and ECC processing is executed in parallel with writing to shorten a cycle time. Moreover, when a memory cell is power-supplied through a well tap, the same address is not assigned while the memory cell is power-supplied through the well tap.

Semiconductor memory device layout comprising high impurity well tap areas for supplying well voltages to N wells and P wells

A semiconductor device comprises, a plurality of memory cells, and an error-correction circuit, wherein write operation is performed by a late-write method, and ECC processing is executed in parallel with writing, and thereby cycle time is shortened. Moreover, it is better that when a memory cell is power supplied through a well tap, the same address is not assigned while the memory cell is power supplied through the well tap.

Semiconductor device

Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

Semiconductor memory device

Semiconductor CMOS memory device with separately biased wells

Semiconductor memory device having bipolar transistor and structure to

A level conversion circuit having a plurality of switching elements connected in series or in parallel to a part thereof and having inputted a plurality of complementary signals to the plurality of switching elements connected in series or in parallel, and a high speed and high driving power switching circuit having a bipolar transistor which is directly driven by an output of such level conversion circuit and which provides level conversion and logic functions.

Switching circuit

A level conversion circuit having a plurality of switching elements connected in series or in parallel to a part thereof and inputted a plurality of complementary signals to the plurality of switching elements connected in series or in parallel, and a high speed and high driving power switching circuit having a bipolar transistor which is directly driven by an output of such level conversion circuit and which provides level conversion and logic functions.

BiMOS current mirror

A semiconductor integrated circuit device in which a wiring layer which supplies a predetermined operation voltage to an electronic circuit has a decreased parasitic impedance. The wiring layer is constituted by a first path and a second path that are connected in parallel between a connection pad and the electronic circuit, or a second wiring layer that constitutes an AC loop is formed close to the first wiring layer which supplies the operation voltage, or the above-mentioned two structures are employed in combination.

Semiconductor integrated circuit device

Current mirror switching circuit

Growing community of inventors

Hamura, Japan

Yoshikazu Saito