Canon Kabushiki Kaisha

Renesas Electronics Corporation

Mitsubishi Chemical Corporation

Leibniz-institut Fuer Neue Materialien Gemeinnuetzige Gmbh

Nihon Parkerizing Co., Ltd.

Denyo Kabushiki Kaisha

Namiki Precision Jewel Co., Ltd.

Leibniz-institut Fur Neue Materialien Gemeinnutzige Gmbh

Yoshikazu Saito

Mitsutoshi Noguchi

Yuichiro Ishii

Norio Ohkuma

Midori Kushida

Etsuko Hino

Carsten Becker-Willinger

Pamela Kalmes

Koji Nii

Helmut Schmidt

Hikaru Ueda

Masaki Tsukude

Shinji Tanaka

Shoji Shiba

Takumi Suzuki

Tetsuya Kosuge

Atsushi Miyanishi

Hiroe Ishikura

Mamiko Kaji

Tsukasa Sano

Makoto Yabuuchi

Tamaki Sato

Takeshi Hashizume

Makoto Moriya

Shinsuke Tsuji

Shunya Nagata

Hidehiro Fujiwara

Masaaki Kiura

Takahiro Mukuda

Masashi Serizawa

Hiroyuki Fukuoka

Masahiko Kubota

Kenji Shinjo

Kazuhiro Asai

Maki Kato

Ryoji Kanri

Akihiko Okano

Toshiaki Sano

Masafumi Morisue

Michael Veith

Yoshisato Yokoyama

Yuichiro Kanasugi

Kouji Harada

Toshi Miyawaki

Ryota Takeuchi

Hirono Yoneyama

Atsunori Yoshida

Hiroshi Nakaya

A semiconductor device includes a memory array arranged in a matrix, a plurality of word lines provided corresponding to memory cell rows, a word driver for driving one of the plurality of word lines, a plurality of row select lines connected to the word driver, and a row decoder for outputting a row select signal to the plurality of row select lines based on input row address information. According to the embodiment, the semiconductor device can detect a failure of the address decoder in a simple method.

Semiconductor device for detecting failure in address decoder

Particles of an acrylic polymer comprising a constituent unit (A) derived from methyl methacrylate and a constituent unit (B) derived from a (meth)acrylic acid alkyl ester in which the alkyl group has 2 to 8 carbon atoms, wherein the particles having electrostatic buildup inhibition rate of 90 to 99.9&#xb0; as obtained by a specific method.

Acrylic polymer particles, production process therefor, ink composition, and coating composition

A porous layer included in a transfer body for image recording by a heat transfer method has a multiple layer configuration, and porous layers are provided such that when a thickness (mm) of each porous layer from a porous layer P(1) of the plurality of porous layers on a side closest to the surface layer to a porous layer P(n) on a side closest to the substrate is set to t(n) (n&#x2265;2), and a total thickness of the transfer body is set to T (mm), Expression (1): C&#xd7;T&#x2264;t(1)+ . . . +t(n) (here, C=0.4, and T&#x2265;1) is satisfied.

Transfer body, image recording method and image recording apparatus

A transfer member for transfer-type image formation according to the present invention includes, in this order, a heat insulating layer, a heat storage layer and a top layer having an image formation surface, and satisfies Expressions 1 to 6: Expression 1: 0.5&#x2264;t&#x2264;1.5 (trepresents the thickness [mm] of the heat insulating layer), Expression 2: 0.05&#x2264;t&#x2264;0.50 (trepresents the thickness [mm] of the heat storage layer), Expression 3: t&#x2264;0.020 (trepresents the thickness [mm] of the top layer), Expression 4: &#x3bb;&#x2264;0.20 (&#x3bb;represents the thermal conductivity [W/(m&#xb7;K)] of the heat insulating layer), Expression 5: &#x3bb;&#x2265;0.23 (&#x3bb;represents the thermal conductivity [W/(m&#xb7;K)] of the heat storage layer), and Expression 6: C&#x2265;1.52 (Crepresents the volume specific heat [MJ/(m&#xb7;K)] of the heat storage layer).

Transfer member, image-forming method and image-forming apparatus

The transfer member for transfer-type inkjet recording of the present invention is formed so that a surface layer includes an organosiloxane compound having a polyalkylene oxide unit and the contact angle of water and the contact angle of hexadecane on the surface are 85&#xb0; or more and 110&#xb0; or less and 25&#xb0; or more and 50&#xb0; or less, respectively.

Transfer member for transfer-type inkjet recording, inkjet recording method and inkjet recording apparatus

A semiconductor memory device including a pair of first bit lines extended in a first direction, a pair of second bit lines extended in the first direction, a first word line extended in a second direction crossing the first direction, a second word line extended in the second direction, a memory cell surrounded by the first bit line, the second bit line, the first word line, and the second word line, and including a drive transistor, a first transfer transistor coupled with one of the pair of first bit lines, and having a gate coupled with the first word line, a second transfer transistor coupled with one of the pair of second bit lines, and having a gate coupled with the second word line, and a load transistor, a write drive circuit that transfers data to the memory cell.

Semiconductor memory device and test method therefor

Particles of an acrylic polymer comprising a constituent unit (A) derived from methyl methacrylic acid and a constituent unit (B) derived from a (meth)acrylic acid alkyl ester in which the alkyl group has 2 to 8 carbon atoms, wherein the particles having electrostatic buildup inhibition rate of 90 to 99.9%.

The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array.

Semiconductor memory device

A test method for a semiconductor memory device having a plurality of memory cells arranged in a matrix form, the test method including writing first data into a plurality of memory cells, while a plurality of word lines disposed in the columns of the memory cells are deselected, driving the low-potential side bit line of a bit line pair in the selected column, which is among a plurality of bit line pairs disposed in the columns of the memory cells, to a negative voltage level in accordance with second data complementary to the first data, and reading the data written into the memory cells.

Provided is a memory macro which allows detection of a fault in a fetch circuit for an address signal which is input. The memory micro includes an address input terminal, a clock input terminal, a memory array and a control unit. The control unit includes a temporary memory circuit which fetches an input address signal which is input into the address input terminal in synchronization with an input clock signal which is input from the clock input terminal and outputs the input address signal as an internal address signal. The memory macro further includes an internal address output terminal which outputs the internal address signal for comparison with the input address signal.

Memory macro and semiconductor integrated circuit device

There is provided an intermediate transfer member used in an image forming method including applying a treatment liquid onto an intermediate transfer member, forming an intermediate image by applying an ink onto the intermediate transfer member coated with the treatment liquid so as to form dots having an average diameter of R, and transferring the intermediate image to a recording medium. The intermediate transfer member includes a surface having recessed portions therein. Each recessed portion allows a circle having a diameter of less than the average diameter R of the ink to be present therein. The surface of the intermediate transfer member has a projected area Sand an actual surface area Ssatisfying the relationship 1.1&#x2264;S/S&#x2264;5.

Intermediate transfer member and image forming method

A semiconductor device having a capability of generating chip identification information includes: an SRAM macro having a plurality of memory cells arranged in rows and columns; a test address storage unit configured to store a test address; a self-diagnostic circuit configured to output the test address based on a result of confirmation of operation of the memory cell selected by the test address; and an identification information generation circuit configured to generate chip identification information based on the test address which is output by the self-diagnostic circuit.

Semiconductor device having capability of generating chip identification information

An intermediate transfer member for use in a transfer-type image recording method including the steps of applying an ink to an intermediate transfer member to form an intermediate image and transferring the intermediate image to a recording medium. The intermediate transfer member includes a surface layer part onto which an ink is applied, the surface layer part containing an organic siloxane compound having a siloxane bond and a polyalkylene oxide unit.

Intermediate transfer member, image recording apparatus, and image recording method

Provided an intermediate transfer member for use in an image forming method including: (1) applying a liquid for reducing fluidity of ink onto the intermediate transfer member; (2) forming an image by applying the ink onto the intermediate transfer member on which the liquid for reducing the fluidity of the ink is applied; and (3) transferring the image onto a recording medium, the intermediate transfer member including: a base; and an elastic layer formed on the base, the elastic layer including: a stack of a first layer being an outer layer and having a plurality of protrusions formed on a surface thereof; and a second layer located below the first layer, an elastic modulus (E1) [MPa] of the first layer and an elastic modulus (E2) [MPa] of the second layer satisfying a relationship of (E1&#x2212;E2)&#x2267;5 [MPa].

Intermediate transfer member, method of manufacturing the same, and image forming method

Growing community of inventors

Tokyo, Japan

Yoshikazu Saito