Mitsubishi Denki Kabushiki Kaisha

Yoshikazu Ohno

Yutaka Inaba

Shinichi Satoh

Hiroki Shinkawata

Junichi Tsuchimoto

Ikuo Ogoh

Masao Nagatomo

Masato Fujinaga

Makoto Hirayama

Takahiro Yokoi

A trench for element separation is formed in a silicon substrate by an etching process using an SiO film as a mask (FIG. B). Side walls are formed in a manner covering the trench laterally (FIG. C). Defect-forming ions such as silicon ions are implanted into the silicon substrate with the SiO film and side walls used as a mask, whereby a gettering layer is formed only at a bottom of the trench

Semiconductor device manufacturing method and semiconductor device

A method of fabricating a semiconductor device is disclosed for connecting a bit line to a semiconductor substrate in a self-aligned fashion in non-contacting relation to a word line and precluding a crystal defect in the semiconductor substrate which might induce a leakage current. An isolation insulative film (2), gate oxide films (3), gate electrodes (4) (word lines), and insulative films (5) are formed on a semiconductor (e.g., Si) substrate (1) in sequential order, and sidewalls (6a to 6f) are formed while substrate protective oxide films (6g to 6i) are formed so that the semiconductor substrate (1) is not exposed. Source/drain regions (261 to 263) are formed, and an insulative film (7) made of Si.sub.3 N.sub.4, SiON and the like is deposited. Then, an interlayer insulative film (8) is formed over the top surface. The insulative film (7) has an etching rate lower than that of the interlayer insulative film (8).

Method of fabricating semiconductor device

A capacitor lower electrode is formed so as to be connected to a main surface of a silicon substrate. The capacitor lower electrode includes a plug portion, a bottom wall portion, and a vertical wall portion. An insulation layer for suppressing crystallization of the vertical wall portion is formed between the bottom wall portion and the vertical wall portion. A capacitor upper electrode is formed on the capacitor lower electrode with a capacitor dielectric layer therebetween.

Semiconductor memory device and fabrication method thereof

A first interlayer insulating layer is formed on a main surface of a substrate. A semiconductor layer is formed on the first interlayer insulating layer. A gate electrode (word line) of a switch MOS transistor is formed under the semiconductor layer. A bit line and a capacitor are formed on the semiconductor layer. The semiconductor layer has a substantially flat upper surface, and an interlayer insulating layer and a second interlayer insulating layer having substantially flat upper surfaces are formed on the semiconductor layer. A capacitor is formed on the second interlayer insulating layer, and the capacitor and the second interlayer insulating layer are covered with a third interlayer insulating layer. Thereby, a level difference between a memory cell array and a peripheral circuitry can be reduced in a semiconductor memory device.

Semiconductor memory device and method of manufacturing the same

A semiconductor device has a memory cell array including MOS transistors and capacitors. Each capacitor include a first capacitor electrode, capacitor dielectric film, and a second capacitor electrode which confronts the first capacitor electrode with the dielectric film interposed therebetween. The first capacitor electrode includes a first-layer electrode having an upper and lower surfaces and a circumferential side surface, and a second-layer electrode which is connected electrically to the lower surface of the first-layer electrode and has a circumferential side surface located inner than the side surface of the first-layer electrode. The capacitor dielectric film is in contact with the upper surface and side surface of the first-layer electrode and spaced out from the side surface of the second-layer electrode. This electrode arrangement suppresses the emergence of a leakage current at the side surface of the second-layer electrode.

Semiconductor device incorporating capacitors

A semiconductor device appropriate for increased integrity in which occurrence of electrical short-circuit between a conductor for connecting a bit line and a semiconductor substrate and a gate electrode is obtained. In this semiconductor device, a first insulation layer, a second insulation layer, and a third insulation layer are formed between a first interconnection layer on the semiconductor substrate and a second interconnection layer. The etching rates of the first insulation layer and the second insulation layer are lower than the etching rate of the third insulation layer.

Semiconductor device having a contact hole

A semiconductor device including a first wiring layer formed on a main surface of a semiconductor substrate, and a first insulating film layer having first and second contact holes which reach the main surface of the semiconductor substrate formed on the first wiring layer. A second wiring layer is formed on the first insulating film layer, and a first electric conductor, connected electrically to the semiconductor substrate, is formed in the first contact hole by self-alignment with respect to the first wiring layer and is isolated electrically from the first wiring layer. A second electric conductor, electrically connecting the second wiring layer to the semiconductor substrate is formed in the second contact hole by self-alignment with respect to the first wiring layer and is isolated electrically from the first wiring layer. A second insulating film layer is formed on the second wiring layer and has a third contact hole which reaches the first contact hole. A first electrode (or third wiring layer), formed on the second insulating film layer and in the third contact hole by self-alignment with respect to the second wiring layer, is electrically connected to the first electric conductor and is electrically insulated from the second wiring layer, since the bit line and gate electrode are not exposed in the contact hole when the contact hole was formed. Therefore, a semiconductor device of high integration is formed without any short circuit between the capacitor electrode and bit line or gate electrode and without any short circuit between the bit line and gate electrode.

Semiconductor device with short circuit prevention and method of

An insulating film is formed on a main surface of a semiconductor substrate. A resist layer is formed on the entire surface of insulating film. An opening is formed in resist layer. By using resist layer as a mask, insulating film is etched, an opening is formed, and then resist is removed. By using insulating film as a mask, an impurity is introduced by ion implantation, and thus an ion-implanted impurity layer is formed. Heat treatment is performed so that ions included in ion-implanted impurity layer are diffused, forming an impurity layer. Etching is performed using insulating film as a mask, and trench is formed with an impurity layer left on the side and bottom surfaces of the trench, which impurity layer serves as a channel stopper. Then, a buried insulating layer is formed in the trench. Consequently, a method of forming an element isolating region is provided by which an impurity layer constituting the element isolating region can be formed minutely with easier control.

Method of forming element isolating region in a semiconductor device

Semiconductor memory device with planarization structure

A cell plate (6) is formed on a main surface of a semiconductor substrate (7) with an insulating film (8) interposed therebetween and an interconnection (1) having T-shape cross section is formed on the cell plate (6) with an interlayer insulating film (11) interposed therebetween. An upper insulating film (12) is formed to cover the interconnection (1).

Growing community of inventors

Hyogo, Japan

Yoshikazu Ohno