Matsushita Electric Industrial Co., Ltd.

Renesas Electronics Corporation

Yoshikazu Nara

Satoshi Tanaka

Manabu Kawabe

Yasuhiko Takahashi

Koji Kasai

Provided are a technique for high-speed switching between clock signals different in frequency, and a clock-control-signal-generation circuit which serves to generate a control signal for clock switching in a clock selector operable to switch between clock signals including a first clock signal based on first and second clock-stop-permission signals and a clock-resume-permission signal. The clock-control-signal-generation circuit includes: a before-switching clock processing unit; and an after-switching clock processing unit. In each of the before-and after-switching clock processing units, the high-frequency clock processing subunit and the low-frequency clock processing subunit take partial charges of processing of clock signals involved in the switching respectively, whereby the processing is speeded up.

Clock control signal generation circuit, clock selector, and data processing device

The present invention aims to efficiently calibrate the characteristics of a pair of reception or transmission low-pass filters by a receiving or transmitting circuit. A semiconductor integrated circuit includes an RF receiver that processes an RF reception signal, an RF transmitter that generates an RF transmission signal and a frequency synthesizer. A reception low-pass filter of the RF receiver suppresses undesired components contained in I and Q baseband reception signals. A transmission low-pass filter of the RF transmitter suppresses noise due to D/A conversion, which is contained in I and Q transmission analog baseband signals. A calibration test signal is supplied to the inputs of the pair of reception or transmission low-pass filters. A difference in phase between the pair of filters is detected by a phase detection unit. A calibration controller calibrates a relative mismatch between the cut-off frequencies of the pair of filters.

Semiconductor integrated circuit

A clock supply apparatus includes a low-rate source clock generating unit for generating a low-rate source clock signal, a frequency multiplication/division unit for performing frequency multiplication/division processing for the low-rate source clock signal to generate a high-rate clock signal to be utilized in signal processing only during a period in which a sleep signal remains nonactive, a sleep time measuring unit for measuring a sleep time duration from the moment the sleep signal becomes active and issuing a sleep end signal upon measurement of a predetermined time period, and a sleep control unit for controlling whether the signal processing block is placed in a sleep or non-sleep mode. The sleep control unit decides the end of the sleep period upon detection of the sleep end signal.

Clock supply apparatus reducing consumption of power

A deinterleaver includes a first storage unit for storing data an order of which is rearranged from a correct order to a random order, a data latching unit for temporarily holding output data of the first storage unit, a second storage unit for storing output data of the data latching unit, and an addressing unit for generating a read addressing signal which is outputted to the first storage unit, and a write addressing signal which id outputted to the second storage unit. The addressing unit includes a counting unit for counting a clock to generate the read addressing signal, and an arithmetic unit for generating the write addressing signal for rearranging to the correct order using the read addressing signal outputted from the counting unit.

Deinterleaver

A zero phase voltage measuring device for measuring a zero phase voltage of the three phase power system having an earth-fault includes an optic voltage sensor provided at any one of three power lines for detecting a current ground-to-line voltage thereat, a line-to-line voltage sensor provided between any two of the three power lines for detecting a current line-to-line voltage therebetween. A phase shifter and a multiplier are provided for calculating an ideal ground-to-line voltage at the power lines when no earth-fault is observed by changing the phase and multiplying the magnitude of the current line-to-line voltage. A subtracter is further provided to obtain a zero phase voltage signal by subtracting the ideal ground-to-line voltage from the current ground-to-line voltage.

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Yokohama, Japan

Yoshikazu Nara