Panasonic Corporation

Nuvoton Technology Corporation Japan

Yoshikazu Makabe

Koji Oka

Toshiaki Ozeki

Ikuo Hidaka

Kazuo Matsukawa

Hitoshi Kobayashi

Keiichi Fujii

Daisuke Nomasaki

Yu Okada

Takeshi Misaku

A battery monitoring device includes a first reference resistor disposed in a path different from a path of current flowing from a battery to a load; a transistor for passing current from the battery to the first reference resistor; and an integrated circuit. The integrated circuit includes: a current measurement unit that measures a first current flowing through the first reference resistor; a voltage measurement unit that measures a first voltage of the battery; and a first calculation unit that calculates an AC impedance of the battery based on the first current measured and the first voltage measured.

Battery monitoring device, integrated circuit, and battery monitoring system

An A/D converter which converts an analog input signal into a digital output signal by performing time-divisional parallel processings on the analog input signal using first and second pipeline type unit A/D converters. The A/D converter sets plural unit A/D converters performing parallel processings according to a system request, such that, when the A/D converter operates with a conversion frequency that is lower than the maximum conversion frequency, the unit A/D converter is halted by a control signal, thereby reducing inter-channel errors among the unit A/D converters to improve the precision of the A/D converter.

A/D converter and A/D conversion method

A first Delayed Flip Flop includes a first D input terminal, a first clock input terminal, a first output terminal outputting a signal inputted to the first D input terminal based on the clock signal, and a first inversion output terminal inverting and outputting the signal inputted to the first D input terminal and outputting the signal to the first D input terminal as a feedback. A second Delayed Flip Flop includes a second D input terminal receiving the output from the first output terminal of the first Delayed Flip Flop, a second clock input terminal, and a second output terminal outputting the signal inputted to the second D input terminal as a first output based on the clock signal. A third Delayed Flip Flop includes a third D input terminal receiving the output from the first inversion output terminal of the first Delayed Flip Flop, a third clock input terminal, and a third output terminal outputting the signal inputted to the third D input terminal as a second output based on the clock signal. The first output and the second output have signal waveforms inverted at the same timing.

Clock signal generating device and analog-digital conversion device

Growing community of inventors

Osaka, Japan

Yoshikazu Makabe