Seiko Instruments Inc

Agency of Industrial Science and Technology

Kabushiki Kaisha Daini Seikosha

Other

Seiko Instruments & Electronics Ltd.

Seiko Seiki Kabushiki Kaisha

Agency Industrial Science

Kogyo Gizyutsuin

Agency of Industrial Science and Technology and Seiko Instruments Inc.

Yoshikazu Kojima

Masaaki Kamiya

Hiroaki Takasu

Kunihiro Takahashi

Tsuneo Yamazaki

Hiroshi Mukainakano

Minoru Sudo

Sadashi Shimoda

Takayuki Takashina

Yutaka Hayashi

Kazutoshi Ishii

Hitoshi Niwa

Nobuyoshi Matsuyama

Jun Osanai

Yutaka Saito

Tadao Iwaki

Kojiro Tanaka

Tomoyuki Yoshino

Satoshi Machida

Yutaka Saitoh

Yukito Kawahara

Yasuhiro Moya

Kentaro Kuhara

Toru Shimizu

Kenji Aoki

Masanori Miyagi

Tadao Akamine

Haruo Konishi

Hiroshi Suzuki

Hiroshi Takahashi

Masahiro Yokomichi

Masaaki Taguchi

Naoto Saito

Naoto Inoue

Shoji Nakanishi

Kiyoaki Kadoi

Satoru Yabe

Ryoji Takada

Kazuaki Kubo

Tetsuya Kaneko

Ryuichi Takano

Masayuki Namiki

Toru Machida

Takao Akiba

Koushi Maemura

Noritoshi Ando

Atsushi Sakurai

Hirofumi Harada

Yukio Suzuki

Kunio Nakajima

Mizuaki Suzuki

Toshiharu Kogure

Katsura Tomotaki

Kazunari Sugiura

Masahiko Kinbara

Michiaki Yazawaw

Yomoyuki Yoshino

Yuichi Kato

Tetsuya Maeda

A semiconductor device including multiple high-voltage drive transistors in its output section is improved in electrostatic withstand voltage by connecting electrostatic protection transistors in parallel with the high-voltage drive transistors connected to the output pads. The drain withstand voltage of the electrostatic protection transistors is made lower than the drain withstand voltage of the high-voltage drive transistors. In addition, the channel length of electrostatic protection transistors is made short to enable efficient bipolar operation of the electrostatic protection transistors.

Semiconductor device and method of fabricating the same

A MISFET is provided with a segmented channel comprising regions in which the channel is inverted by a first gate voltage and regions in which the channel is inverted by a second gate voltage. The MISFET is formed in a semiconductor substrate having a first conductivity type and the first inversion region of the channel has a first impurity concentration determined by the surface concentration of the substrate. The second inversion region of the channel has a second impurity concentration determined by doping an impurity to the region selected by a photolithographic process. The first and second inversion regions may be divided into a plurality of plane shapes and the threshold voltage of the MISFET is set to a desired value in accordance with the plane area ratio of the first and second inversion regions.

Semiconductor device and manufacturing method thereof

To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.

Semiconductor integrated circuit and manufacturing method therefore

A method for producing a semiconductor temperature sensor comprises the steps of forming PNP bipolar transistors and PMOS transistors so that a base region of each of the PNP bipolar transistors and a corresponding N-well region of each of the PMOS transistors are formed at the same time, and connecting the PNP bipolar transistors in a Darlington connection.

Method for producing semiconductor temperature sensor

In a semiconductor integrated circuit device having laser-trimmable fuses and a trimming position pattern, in order to increase trimming accuracy and reduce the size of the positioning pattern, the fuses and the positioning pattern are formed using the same thin film. The trimming positioning pattern has an abrupt boundary between a high light reflectivity region and a low reflectivity region so that light reflectivity varies abruptly. To further reduce size, the trimming positioning pattern can be formed in pad areas of a integrated circuit chip or placed at intersections between scribe lines in a wafer.

Semiconductor device having trimmable fuses and position alignment marker formed of thin film

In a MISFET, areas where a channel surface of a channel region is inverted by a first gate voltage and areas where the channel surface is inverted by a second gate voltage are provided in the channel region of the MISFET in plane as components thereof. The channel region,having a first impurity concentration determined by a surface concentration of a P-type semiconductor substrate and a channel region,having a second impurity concentration determined by doping an impurity to the region selected by a pattern,of a mask for doping impurity by ion implantation and others are provided in a channel region of an N-type MOSFET on the P-type semiconductor substrate. The channel region,having the first impurity concentration and the channel region,having the second impurity concentration are divided into a plurality of plane shapes. The channel region of the same MOSFET may be structured by the plurality of plane shapes having the plurality of impurity concentrations as described above and a threshold voltage of the MOSFET may be readily set to a desired value in response to a plane area ratio of the area having the first impurity concentration and the area having the second impurity concentration, allowing to realize a high performance semiconductor integrated circuit device at low cost.

A linear image sensor IC comprising a plurality of switching circuits each connected to a plurality of light receiving elements in series; scanning circuits for sequentially switching said switching circuits; and driving circuits for operating said scanning circuits, wherein a LOCOS isolation layer is formed between an edge in the main scanning direction of the linear image sensor IC which is closest to an array of the light receiving elements and a light receiving portion of the light receiving element. The inventive image sensor IC is mounted by devising so that the circuit can be put into a thin and long pattern in the scanning direction, so that the chip having a width thinner than a thickness thereof which had been beyond expectation by the prior art can be realized. The use of this very thin IC allows a compact IC assembling substrate having less fluctuation among ICs to be manufactured at low cost. Even more, it becomes possible to mount ICs readily on a cylindrical substrate which had been also difficult in the past. Thereby, electronic devices such as a compact and low cost multi-chip type image sensor or multi-chip type thermal head can be realized. Accordingly, it becomes possible to bring down the cost thereof, which had been difficult in the past, and to realize a low cost facsimile.

Linear image sensor device, IC assembling substrate and method for assembling the same

A charge/discharge control circuit is provided for an electric power source apparatus in which a service life is prolonged. A voltage dividing circuit, an overcharge voltage detection circuit, an overdischarge voltage detection circuit and a control circuit are connected in parallel to a secondary cell which is an electric power source, wherein the control circuit detects a condition of the secondary cell from the overcharge/overdischarge voltage detection circuits and outputs a signal Vs for controlling a power supply to an external equipment and a charge by an external power source and controls a switching element provided in series with the voltage dividing circuit and reduces a current which flows through the voltage dividing circuit.

Charge/discharge control circuit and chargeable electric power source apparatus

Small geometry high voltage semiconductor device

To provide a semiconductor substrate and a light-valve semiconductor substrate capable of preventing the threshold value of a MOS transistor on a single-crystal silicon device forming layer from increasing and forming a MOS integrated circuit with a high reliability even for a long-time operation. A semiconductor substrate and a light-valve semiconductor substrate comprising a single-crystal silicon thin-film device forming layer,formed above an insulating substrate,through an adhesive layer,and an insulating layer,formed on the single-crystal silicon thin-film device forming layer, wherein a heat conductive layers,and,made of a material with a high heat conductivity are arranged between the single-crystal silicon thin-film device forming layer and the adhesive layer and on the insulating layer.

Semiconductor device

An low-power consumption integrated ring oscillator capable of stable operation throughout a wide voltage range without undergoing a large frequency change includes a first constant voltage generating circuit having an enhancement mode P-MOS transistor and a depletion mode N-MOS transistor and a second constant voltage generating circuit having a depletion mode N-MOS transistor and an enhancement mode N-MOS transistor. A first constant voltage generated by the first constant voltage circuit is applied to a gate electrode of a P-MOS transistor of transmission gates connected between respective cascaded inverters of the ring oscillator. A second constant voltage generated by the second constant voltage generating circuit is connected to the gate electrode of an N-MOS transistor of the transmission gates. By this construction, current consumption is reduced and battery lifetime can be increased. The boosting circuit for writing and erasing an EEPROM circuit may be formed with the low power ring oscillator.

Low power oscillation circuit and non-volatile semiconductor memory having ring oscillator

A semiconductor substrate is utilized to integrally form a drive circuit and a pixel array to produce a transparent semiconductor device for a light valve. The semiconductor device for a light valve is constructed of a semiconductor substrate composed of a bulk single crystal silicon having an opaque thick portion and a thin transparent portion. A pixel array is formed in the transparent portion. A drive circuit is formed in a top face of the opaque portion. A transparent support substrate is laminated to the top face of the semiconductor substrate for reinforcement. A bulk portion of the semiconductor substrate is removed from a back face thereof by selective etching to provide the transparent portion.

Method of forming a semiconductor device for a light valve

Overcharge/overdischarge detecting circuit having current detecting means with latch function and chargeable electric power source apparatus

Overcharge/overdischarge detecting circuit having a reset means and

In a method of manufacturing a semiconductor chip, a wire is traveled in one way to cut a wafer into a plurality of chips while a wire train where wires are arranged by pitches of scribe lines is brought into contact with the scribe lines of the wafer linearly, and an abrasive solution is supplied to a contact portion thereof.

Method of manufacturing a semiconductor chip

Growing community of inventors

Tokyo, Japan

Yoshikazu Kojima