Mitsubishi Denki Kabushiki Kaisha

Yoshikazu Kamitani

Motoi Ashida

Eiji Hamasuna

Kazuhito Tsutsumi

Hideaki Nagaoka

Satoshi Arima

Yoshiyuki Haraguti

A driver transistor including a gate electrode is formed on the surface of a p well of a silicon substrate. A silicon oxide film and a silicon nitride film are formed to cover the driver transistor. An interlayer insulator film is formed on the silicon nitride film. A contact hole is arranged to planarly overlap with at least the gate electrode. Thus, a semiconductor device capable of performing desired operations and reducing a memory cell area is obtained.

Semiconductor device

A predetermined reticle is used for sequentially irradiating (giving a shot of) an exposure light onto a negative resist. In the negative resist the region irradiated with the exposure light remains as a resist pattern. The exposure light is not irradiated onto the negative resist in the wafer outer peripheral region. After that, a negative resist pattern is formed by carrying out a development process and, by using this as a mask, etching is carried out on the first conductive layer and, thereby, the first metal wire layer is formed. Since no resist pattern is formed in the wafer outer peripheral region, the first conductive layer does not remain. Thereby, a semiconductor device wherein a conductive layer is prevented from scattering off at the time of the dicing of the wafer can be gained.

Method of manufacturing semiconductor device as well as reticle and wafer used therein

A semiconductor device having a conductive layer of small conductive resistance and including only a small step is provided. The semiconductor device comprises a first source line extending in one direction and a silicon oxide film having a contact trench reaching the first source line. The contact trench extends in one direction along the first source line. The semiconductor device further comprises a second source line which is formed in the contact trench. A part of the second source line exposes a partial surface of the first source line to be in contact with this partial surface of the first source line.

Semiconductor device with a conductive layer of small conductive resistance

A shared contact is provided on the side of a drain active region of each of two load transistors. Thus, a stabilized low voltage operation is ensured in a full CMOS type SRAM memory cell having the shared contact.

Growing community of inventors

Hyogo, Japan

Yoshikazu Kamitani