Fujitsu Corporation

Yoshikazu Iwami

Takayuki Kinoshita

Hidekazu Osano

Makoto Hataida

Toshikazu Ueki

Hideyuki Sakamaki

An error check apparatus including, a packet protocol error check processing circuit configure to detect a protocol error of a packet, a retry control circuit configured to receive the protocol error of the packet from the packet protocol error check processing circuit, and to perform request for retry for data of the packet if the received protocol error has not been detected from a packet retransmitted by retry request, and an error notification circuit configured to notify of the protocol error of the packet to a processing unit in a higher-level layer if the protocol error is not a first protocol error for the packet.

Apparatus and method for error check of transmission data

An arbitration method includes a first process to perform a path control to transfer data from physically plural input ports logically having plural virtual channels to an arbitrary one of the plural output ports, wherein only one channel is selectable at one input port at an arbitrary point in time, by performing an arbitration among the channels of each of the plural input ports according to an arbitrary arbitration algorithm other than a time-division algorithm, and a second process to perform an arbitration among the plural input ports according to the arbitrary arbitration algorithm. The arbitrary arbitration algorithm used in the first and second processes is switched to the time-division algorithm for a predetermined time in response to a trigger.

Arbitration method, arbiter circuit, and apparatus provided with arbiter circuit

A debug system scans a scan memory element group having a plurality of scan memory elements which are connected in series in a semiconductor integrated circuit device and collects data in the scan memory element group. The semiconductor integrated circuit device has an end code register which is provided between an input terminal and an input side of the scan memory element group and holds an end code, a start code register which is provided between an output terminal and an output side of the scan memory element group and holds a start code, and a scan control circuit which controls shift operations of the scan memory element group, the end code register and the start code register, and outputs scan data to the output terminal.

Semiconductor integrated circuit device, method of controlling the semiconductor integrated circuit device and information processing system

A linkup state generating method for generating a state in which linkup is completed in first and second information processing apparatuses, the first and second information processing apparatuses each including a linkup function of, with parameter exchange, comparing parameters included in the first and second information processing apparatuses and adjusting specifications of the parameters so that the specifications of the parameters match each other, the linkup state generating method including setting, from the outside, a parameter in the first information processing apparatus so that a specification of the parameter included in the first information processing apparatus matches a specification of a parameter included in the second information processing apparatus, and sending, from the first information processing apparatus, a signal received from the second information processing apparatus to the second information processing apparatus in a manner that the second information processing apparatus recognizes that parameter exchange has been performed.

Linkup state generating method, information processing apparatus, and linkup state generating program

An arbitration device including: a first measuring circuit to measure a first period; a second measuring circuit to measure a second period; a second selection circuit to select and output the first period or the second period according to a first selection signal; a first control circuit to output the first selection signal according to the first period and the second period; a third selection circuit to select a third data or either the first data or the second data according to a second selection signal; a third measuring circuit to measure a third period; a fourth measuring circuit to measure a fourth period; and a second control circuit to output the second selection signal according to either the selected first period or the selected second period and the third period and the fourth period.

Arbitration device that arbitrates conflicts caused in data transfers

A scan control method for a circuit device connected with a first bus and having a test access port controller, including setting information indicating a register to be scanned in the circuit device, a number of scan shifts and a scan start via a second bus different from the first bus, and generating based on the information set, by using a sequencer, a signal replacing a test mode signal and a test reset signal transferred via the first bus during testing of the circuit device, and supplying the signal to the test access port controller.

Scan control method, scan control circuit and apparatus

A scan control method of a circuit device including setting information indicating scan mode in a register is provided. The scan control method includes cutting an output of scan-out data to a test access port controller and an input of scan-in data from a data register based on information set in the register, and controlling a connection between a scan register and a data register. Each data/scan register includes data registers for the same number of chains to be scanned at the same time. Data set in one data register may be kept in all the data registers in parallel and scanned in all the scan chains in a scan-in process in the broadcast mode. The data set in the data register may be kept in the data register corresponding to the scan register and scanned in the corresponding scan chain, in a scan-in process in the parallel mode.

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Kawasaki, Japan

Yoshikazu Iwami