Sanyo Electric Co., Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Yoshikazu Ibara

Yasunori Inoue

Shinichi Tanimoto

Kiyoshi Yoneda

Koichi Saito

Atsuhiro Nishida

Tatsuhiko Koide

Daichi Suma

Kazutoshi Tsujimura

Toyozou Nishida

Yasuhiko Yamashita

Yoshio Okayama

Kazuhiro Sasada

A solar cell module includes an encapsulating member and a sealing layer for sealing a solar cell, and further includes a solar cell having a transparent conductive layer on its front surface. The solar cell includes a coating layer formed over the transparent conductive layer and having a plurality of openings, and a collecting electrode positioned in the openings of the coating layer and including a primary conductive layer containing copper. An undercoat layer is provided between the primary conductive layer of the collecting electrode and the transparent conductive layer. The coating layer and the undercoat layer are both composed of a resin.

Solar cell, solar cell module, and method for manufacturing solar cell

A solar cell has a collecting electrode formed therein. The collecting electrode is provided with: a main conductive layer that contains copper; and an overcoat layer that covers at least a part of the main conductive layer.

A semiconductor device manufacturing method including forming a conductive layer and a silicon film on a semiconductor substrate including an active region, forming an emitter electrode containing a first impurity on the silicon film above the active region, partially etching the silicon film using the emitter electrode as a mask, forming an insulative film covering the semiconductor substrate and a side wall film covering a side surface of the emitter electrode, introducing a second impurity into the conductive layer and silicon film so that the second impurity reaches the active region to form an impurity region containing the second impurity in parts of the conductive layer and silicon film, and diffusing the first impurity contained in the emitter electrode into the silicon film to form in the silicon film a first region containing the first impurity and a second region free of the first impurity.

Manufacturing method for semiconductor device

A high capacity semiconductor device having a narrowed emitter layer. The semiconductor device includes a collector layer formed on a semiconductor substrate. An SiGe alloy layer is formed on the collector layer. A silicon film is formed on the SiGe layer. An emitter electrode is formed on the silicon film. A side wall film covers the side surface of the emitter electrode. The bottom surface of the emitter electrode is located above the lower surface of the side wall film. Part of the second region of the silicon film is located between the SiGe alloy layer and the side wall film. An impurity region is formed adjacent to the conductive layer. A silicide film is formed along the side surface of the second region, the side surface of the conductive layer, and the surface of the impurity region.

Semiconductor device

A method of fabricating a semiconductor device capable of suppressing defective etching in formation of a deep trench also when the number of polishing steps is reduced is obtained. This method of fabricating a semiconductor device comprises steps of forming a first trench on an element isolation region of a semiconductor substrate, forming a first film consisting of an insulator film to fill up the first trench, forming a second trench larger in depth than the first trench in the first trench, forming an embedded film in the second trench and substantially simultaneously polishing an excess depositional portion of the first film and an excess depositional portion of the embedded film.

Method of fabricating semiconductor device

A semiconductor device capable of easily setting the sheet resistance of a resistive element or the like to an arbitrary value is obtained. This semiconductor device comprises a first silicide film formed on a first silicon region and a second silicide film, formed on a second silicon region, consisting of the same silicide material as the first silicide film and differing from the first silicide film in film quality to have a sheet resistance value different from that of the first silicide film. When an impurity is introduced into the second silicide film itself so that the second silicide film differs from the first silicide film in film quality in this case, for example, a second silicide film having an arbitrary high sheet resistance value can be obtained by controlling the type of and an introduction condition for the impurity.

Semiconductor device having silicide films

A semiconductor device capable of effectively preventing defective short-circuiting across a gate electrode and an impurity region and reducing the resistance of the gate electrode and the impurity region is provided. In this semiconductor device, a first gate film is formed on a channel region through a gate insulator film. A second gate film consisting of a first compound layer is formed on the first gate film. A second compound layer is formed on the surface of the impurity region. A reaction preventing film for preventing the first compound layer and the second compound layer from reacting with each other is formed on the second gate film. The first and second compound layers are formed independently of each other without reaction in the process of formation due to the reaction preventing film. Thus, defective short-circuiting across the gate electrode and the impurity region is effectively prevented while process tolerance is increased.

Semiconductor device with reduced short circuiting between gate electrode and source/drain region

A method of manufacturing a semiconductor device capable of suppressing increase of a leakage current resulting from a high-temperature heat treatment is obtained. In this manufacturing method, an impurity region is formed by selectively ion-implanting an impurity into the main surface of a semiconductor substrate. The impurity region is activated by performing a high-temperature heat treatment. The semiconductor device is recovered from crystal defects resulting from the high-temperature heat treatment by performing a low-temperature heat treatment after performing the high-temperature heat treatment. According to this manufacturing method, the semiconductor device is recovered from the crystal defects resulting from the ion implantation by the high-temperature heat treatment, and recovered from the crystal defects resulting from the high-temperature heat treatment by the low-temperature heat treatment. Thus, increase of a leakage current caused by the crystal defects resulting from the high-temperature heat treatment can be effectively prevented.

Method for forming low-leakage impurity regions by sequence of high-and low-temperature treatments

A semiconductor device suitable for increasing operation speed and microminiaturization is provided. First and second impurity diffusion regions are formed sandwiching an element isolation insulation film. After a metal film is deposited all over a substrate, a heat treatment for silicidization is applied to form a metal silicide layer on the first and second impurity diffusion regions. The metal film not silicided is removed by etching with a predetermined region of the metal film on the two metal silicide layers and on the element isolation insulation film covered with a mask. The metal silicide layers on the first and second impurity diffusion regions are electrically connected by a metal interconnection layer that is not silicided and that extends on and in direct contact with the element isolation insulation film.

Semiconductor device and fabrication method thereof

A semiconductor device includes an insulating layer and an interconnection layer having a conductive layer provided over the insulating layer. The interconnection layer is patterned by photolithography. The device further includes a cap-metal layer, which is deposited on the conductive layer and suppresses reflection of light beams at the time of patterning the interconnection layer. The cap-metal layer has any one of the following structures: a double-layered structure having a titanium nitride layer and a titanium layer located between the titanium nitride layer and the conductive layer; a double-layered structure having a titanium nitride layer and an aluminum-titanium alloy layer located between the titanium nitride layer and the conductive layer; and a single-layered structure consisting essentially of an aluminum-titanium alloy. These design ensure accurate interconnection patterning in the photolithography, and provide improved EM and SM immunities of the interconnection.

Semiconductor device having cap-metal layer

A semiconductor device is disclosed, which includes an insulating layer and an interconnection layer having a conductive layer provided over the insulating layer. The interconnection layer is patterned by photolithography. The device further includes a cap-metal layer, which is deposited on the conductive layer and suppresses reflection of light beams at the time of patterning the interconnection layer. The cap-metal layer has any one of the following structures: a double-layered structure having a titanium nitride layer and a titanium layer located between the titanium nitride layer and the conductive layer; a double-layered structure having a titanium nitride layer and an aluminum-titanium alloy layer located between the titanium nitride layer and the conductive layer; and a single-layered structure consisting essentially of an aluminum-titanium alloy. These design ensure accurate interconnection patterning in the photolithography, and provide improved EM and SM immunities of the interconnection.

Growing community of inventors

Gifu, Japan

Yoshikazu Ibara