Fujitsu Corporation

Yoshikazu Homma

Tetsuji Takeguchi

Mitsutaka Ikeda

Tsutomu Taniguchi

The present invention provides a semiconductor memory device that performs a highly reliable data read operation at a high speed. This semiconductor memory device reads data stored in memory cells in accordance with a result of a comparison between a signal read out from the memory cells, which are connected to a word line, with a signal read out from a reference cell connected to a reference word line. This semiconductor memory device includes a load capacity adjustment circuit that adjusts the timing of starting up the gate of the reference cell in accordance with each location of the connection of the memory cells to the word line.

Semiconductor memory device having a resistance adjustment unit

Semiconductor device having a high-speed data read operation

Semiconductor memory device having high speed data read operation

It is judged whether or not the output voltages of a memory cell and a first reference cell, which is for outputting a voltage at a first reference level to be compared with the output voltage of the memory cell, have reached their respective comparable levels, on the basis of the output voltages of first to third reference cells. After voltage values which can be compared with each other are obtained, the comparison result of the output voltage of the memory cell with the output voltage of the first reference cell is stored in a first latch circuit as the stored data of the memory cell, and the data is output via an output buffer. Thus, even when a reduction of an internal power supply voltage occurs, the data stored in the memory cell can be properly output.

Read device and read method for semiconductor memory

A semiconductor memory device comprises a detecting unit and a testing unit. The detecting unit detects a plurality of times a state of a predetermined terminal when the power is switched on, and activates the testing unit when all results of the detections show expected values. The device shifts to a connection testing mode by activation of the testing unit, and performs predetermined testing. Therefore, the testing can be performed by causing the device to shift to the testing mode without using terminals dedicated to testing. Besides, a shift to the connection testing mode by activation due to an erroneous operation or power-supply noise is prevented from occurring. In another semiconductor memory device the conversion circuit receives parallel testing patterns via a plurality of input terminals and converts the patterns into serial output patterns. Since the parallel testing patterns are converted into serial output patterns, connection testing can be performed even when the number of output terminals is small. Furthermore, another semiconductor memory device comprises an operation circuit and a conversion circuit. The operation circuit receives parallel testing patterns via a plurality of input terminals, performs a logic operation, and outputs parallel operation result patterns. The conversion circuit receives the parallel operation result patterns and converts the patterns into serial output patterns. The converted output patterns are sequentially output from output terminals. The testing patterns fed to the conversion circuit by the operation circuit can be reduced. Accordingly, the output patterns become shorter, and testing time is reduced.

Semiconductor memory device, circuit board mounted with semiconductor memory device, and method for testing interconnection between a semiconductor memory device with a circuit board

Growing community of inventors

Kawasaki, Japan

Yoshikazu Homma