Sanyo Electric Co., Ltd.

Yoshikazu Asano

Kazuo Naganawa

Yoshihiro Hori

Shuji Yanase

Yosuke Mizutani

A MUSE sound decoder detects a broadcasting/non-broadcasting identification flag included in the control signals in an applied MUSE signal to determine whether the MUSE signal is broadcasted or non-broadcasted. The MUSE sound decoder further includes a frame synchronization protection circuit for protecting frame synchronization over a predetermined frame synchronization protection time period when the frame synchronization pattern is not detected at the proper timing. The frame synchronization protection circuit sets the frame synchronization protection time period to a long time period when the MUSE signal is determined to be a broadcasted MUSE signal, and to a short time period when the MUSE signal is determined to be a non-broadcasted MUSE signal. Appropriate muting of a sound signal can be carried out according to the condition of the received MUSE signal.

Broadcast/non-broadcast MUSE signal sound decoder with a variable

A convertor for converting a sub-sample television signal such as MUSE signal, which is obtained from a high density television signal by way of offset sub-sampling the horizontal scan lines of the high density television signal and time compressing the transmission band, to a standard television signal includes odd field and even field vertical filters for filtering odd lines and even lines in the MUSE signal, and time base expanders for selecting predetermined lines from the lines filtered by the odd and even field vertical filters and for expanding on time base the selected predetermined lines. Also, another vertical filter is provided for processing the signal from the time base expanders according to the sub-sampling phase.

Television signal convertor

A frame synchronizing signal detecting circuit detects a frame synchronizing signal in a video signal. When the frame synchronizing signal is not detected by the frame synchronizing signal detecting circuit, a clamp level switching circuit is responsive to a switching signal from a timer circuit for generating alternately an upper clamp potential V.sub.+ and a lower clamp potential V.sub.-. When the frame synchronizing signal is detected by the frame synchronizing signal detecting circuit, the clamp level switching circuit generates a normal clamp potential V.sub.0. A clamping pulse generating circuit is responsive to an output from the frame synchronizing signal detecting circuit for generating a clamping pulse. A clamping circuit is responsive to the clamping pulse for clamping an analogue video signal at the clamp potentials V.sub.0, V.sub.+ or V.sub.- from the clamp level switching circuit.

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Kakamigahara, Japan

Yoshikazu Asano