Fujitsu Corporation

Yoshikatsu Kouhara

Kouichi Tanda

Hiroaki Shiraishi

Koji Takatomi

Takakazu Tokunaga

Yoshinori Soejima

Akitsugu Nakayama

Hiroaki Miyamoto

Noritoshi Yamakawa

A computer terminal retrieves pin data related to respective pins of a plurality of Field Programmable Gate Array that are mounted on a board. The computer terminal retrieves setting data related to a connection check. Upon retrieving the pin data and the setting data, the computer terminal assigns, as data for the connection check to all the pins that can output data, unique data that is unique to each pin. The computer terminal generates input pin data and output pin data containing the unique data, stores therein the input pin data and the output pin data, and generates checking circuits that check connections between output pins and input pins. The computer terminal generates checking data based on the checking circuits.

Data generating method, connection checking system, and computer product

A logical memory construction-processing section reads several kinds of physical memories and registers prepared in advance as libraries, generates candidates for each logical memory, by combining only the physical memories or only the registers, or both the physical memories and the registers, with each other, so as to construct the logical memory that satisfies a logical condition defining a memory space, and selects highest priority candidates for the logical memories from the candidates according to priorities. An optimum construction extraction-processing section extracts optimum logical memories satisfying the respective logical conditions from the highest priority candidates such that the limit numbers of usable physical memories and usable registers are satisfied. A circuit description-processing section executes circuit description by using the physical memories and the registers that construct each of the extracted optimum logical memories, to thereby generate a circuit description file.

Memory construction apparatus for forming logical memory space

A method and apparatus for generating file information including setting clock information regarding a clock condition and a clock speed to be used by a speed conversion circuit block, reconstructing the clock circuit block including a new clock for accommodating insertion of the speed conversion circuit block, and associating connection terminal information indicating a connection relationship of connection terminals with speed conversion object information having set, as a speed conversion object, a connection terminal requiring connection speed conversion. The connection terminal information of the connection terminal set as the speed conversion object is extracted, speed conversion circuit information indicating a connection relationship of the connection terminals in the speed conversion circuit block and connection terminal information having the connection relationship of the connection terminals reconstructed is generated, and file information in which the speed conversion circuit block is inserted between the clock circuit block and the interface block is generated.

File information generating method, file information generating apparatus, and storage medium storing file information generation program

A computer is allowed to execute an information acquisition process that acquires a file expressing information on pins used in respective ports provided in each block of a logic circuit to be redesigned and information indicating connection relationships between the ports (#); execute a multiplexer disposition process that, based on the file, classifies pins of output ports of a block into a number of pin groups that is less than the number of pins, and disposes a multiplexer having a function to multiplex a signal output from each pin classified in the same pin group (#); and execute a demultiplexer disposition process that, based on that file, disposes a demultiplexer having a function to demultiplex signals that have been output from output ports of a block and multiplexed by the multiplexer, and a function to output each demultiplexed signal to input ports of respective input destination blocks (#).

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Fukuoka, Japan

Yoshikatsu Kouhara