Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Engineering Company, Limited

Yoshiji Inoue

Takehiko Umeyama

Masayoshi Shimamoto

Yasuhiro Okazaki

Kenji Goto

Manabu Tsukamoto

Kouji Takahashi

In an optical information reproduction method and apparatus with a tracking servo system using a tracking error signal in the phase difference method, the effect of the offset which varies depending on the pit depth and the lens position can be corrected and a tracking error detecting means free from the offset can be obtained. To this end, the phase comparison means are made to receive a certain set of input signals during the offset correction, and a different set of input signals during the tracking error signal detection. The offset in the tracking error signal which varies depending on the pit depth and the lens position is obtained as a voltage value, and through repeated learning control, this offset is corrected.

Method of and apparatus for optical information reproduction

In an optical information reproduction device for reproducing information from an optical disk medium on which an identification information area including first identification information shifted radially outward with respect to the center of a recording track by a specified distance and second identification information shifted radially inward with respect to the center of a recording track by a specified distance, and a user information area disposed along the center of a recording track are disposed, information is reproduced using a sum signal and a difference signal of the outputs from a split photodetector having at least two light-receiving parts disposed on opposite sides of a track tangential line. The first or second identification information signal is inverted and the direct-current component in the identification information signal and the user information signal are removed.

Optical information reproduction device and signal processing circuit used therein

A master-slave flip-flop circuiting having transistors connected in cascade in two stages between a power supply and ground. A clock differential amplifier, a master flip-flop, a slave flip-flop, and a waveform-shaping amplifier are all connected mutually in parallel to a power supply. High-speed operation at a minimum operation power supply voltage is achieved.

Master-slave flip-flop circuit

A comparator compares phases of an input data supplied from an input terminal and a synchronizing clock signal output by a variable counter, and outputting a comparison result signal indicative of any of a 'lead', a 'lag' and a 'non-detection' of the edge of the input data with respect to the up edge of the synchronizing clock signal. A state detector circuit detects the numbers of 'leads' and 'lags' in comparison result signals output by the comparator, and outputting a state detected signal indicative of any of 'the number of leads is larger', 'the number of lags is larger' and 'the number of leads is equal to the number of lags'. A dividing ratio selection circuit outputs a dividing ratio signal indicative of any of a 'dividing ratio smaller than a reference dividing ratio', a 'dividing ratio greater than the reference dividing ratio' and the 'reference dividing ratio', based on the comparison result signals output by the comparator and state detected signals output by the state detector circuit. A variable counter divides the frequency of a reference clock signal in response to the dividing ratio signal output by the dividing ratio selection circuit and outputs the result of the division to the comparator and an output terminal.

Clock signal generator and data signal generator

A switching circuit operable under a low voltage power source includes first and second level shift circuits. The level shift circuits receive a switching control signal and generate an internal switching signal and an inverted internal switching signal. The level shift circuits supply the internal switching signals to switching elements. A switched capacitor filter includes an amplifier and the described switching circuit. The amplifier has amplification inverters connected in series in three stages.

Switching circuit and switched capacitor

This invention provides a peak signal detecting device by which a peak of an input signal can be accurately detected even if a noise is caused. A level slice circuit (3) outputs a level slice signal S3 which turns to High/Low depending upon whether an absolute value of a reading signal S0 is more/less than a threshold value VT1. A level slice circuit (5) outputs a level slice signal S5 which turns to High/Low depending upon whether an absolute value of a differentiated signal S1 is more/less than a threshold value VT2. A delay circuit (6) delays a leading edge of the level slice signal S5 for a period T1 and its trailing edge for a period T2 to produce a delay signal S6. At this time, this process is cancelled when the High level of the level slice signal S5 is less than T1. A gate circuit (4) outputs a conjunction of a zero cross signal S2, level slice signal S3 and delay signal S6 as a gate signal S4' (peak detecting signal).

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Tokyo, Japan

Yoshiji Inoue