Micron Technology Incorporated

Yoshihito Morishita

Chikara Kondo

Takamasa Suzuki

Katsuhiro Kitagawa

Hiroshi Ichikawa

Daigo Toyama

Devices and methods for operating a low-power memory device includes a first data input (DQ) circuitry including an input buffer configured to generate a loopback data signal based at least in part on a data signal received at the first DQ circuitry when the low-power memory device operates in a feedback mode. A second DQ circuitry includes an output buffer configured to receive the loopback data signal from the first DQ circuitry and to output the loopback data signal via a data pin.

Loopback circuit for low-power memory devices

Systems and techniques to offset conditions affecting propagation delay of a clock signal in a memory device. These include a device that includes a clock adjustment circuit, comprising a differential amplifier, an inverter coupled to a first output of the differential amplifier, and a swing oscillator driver coupled to a second output of the inverter and an input of the differential amplifier. The swing oscillator driver includes a series of transistors, a signal path coupled to at least a first transistor of the series of transistors, wherein the signal path when in operation transmits a signal having a first voltage, and a strength control circuit coupled to the signal path, wherein the strength control circuit when in operation adjusts the first voltage of the signal to a second voltage.

Systems and techniques for timing mismatch reduction

Disclosed herein is an apparatus that includes a memory cell array; a data input/output terminal; a read data path and a write data path coupled in parallel between the memory cell array and the data input/output terminal, wherein the read data path includes a pre-driver and an output driver coupled in series, and wherein the write data path includes an input receiver and a latch circuit coupled in series; and a test path configured to provide a shortcut between the pre-driver in the read data path and the latch circuit in the write data path.

Semiconductor device performing loop-back test operation

Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.

Apparatuses, systems, and methods for system on chip replacement mode

Apparatuses, systems, and methods for fuse based device identification. A device may include a number of fuses which are used to encode permanent information on the device. The device may receive an identification request, and may generate an identification number based on the states of at least a portion of the fuses. For example, the device may include a hash generator, which may generate the identification number by using the fuse information as a seed for a hash algorithm.

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Shibuya-ku, Japan

Yoshihito Morishita