Kabushiki Kaisha Toshiba

Yoshihisa Sugiura

Yoshihisa Iwata

Takashi Suzuki

Kenichi Imamiya

Atsushi Inoue

Tamio Ikehashi

Ken Takeuchi

Tatsuya Tanaka

Takashi Mori

Yasuo Itoh

Tomoharu Tanaka

Koji Sakui

Yoshiyuki Tanaka

Hiroshi Watanabe

Junichi Miyamoto

Sumio Tanaka

Masaki Momodomi

Toshio Yamamura

Keniti Imamiya

Kazuhisa Kanazawa

A nonvolatile semiconductor memory has a first memory chip set so as to be operated by specifying the chip address upon reset; and a second memory chip set so as not to be specified by the chip address and not to be operated upon reset, the first memory chip and the second memory chip each comprising a power-on reset circuit which detects a power supply voltage after power-on and outputs a reset signal for resetting an operation when the power supply voltage is equal to or higher than a predetermined value.

Nonvolatile semiconductor memory

A non-volatile semiconductor memory is disclosed, which comprises a plurality of memory cell arrays each having a number-of-rewrites storage region allocated to a portion of a corresponding cell array, and a number-of-rewrites write control circuit which stores the number of rewrites in cell transistors of the number-of-rewrites storage regions in non-selected memory cell arrays of the plurality of memory cell arrays by executing write of data to the cell transistors at a voltage lower than an ordinary write voltage so as to change a threshold value of the cell transistors in analog fashion according to an amount of electrons injected into floating gates of the cell transistors.

Non-volatile semiconductor memory

A semiconductor integrated circuit device includes a non-volatile memory having a pseudo pass function of returning a pass as a status even if a bit error reaching an allowable number of bits occurs after at least one of write or erase sequence is completed. The non-volatile memory includes an issue timing control section for controlling timing of issuing the pseudo pass function.

Semiconductor integrated circuit device and non-volatile memory system using the same

A semiconductor memory device is disclosed, which includes a memory cell array including a plurality of memory cells, a built-in self-test circuit which writes test pattern data including binary 0 and binary 1 in the memory cells in units of a page to perform a test for the memory cells, a plurality of sense amplifiers which hold a plurality of data read from the memory cells in units of a page, and a detection circuit which collectively detects the plurality of data held by the sense amplifiers and outputs a detection result to the built-in self-test circuit.

Semiconductor memory device

A non-volatile memory system comprises a non-volatile memory and a memory controller controlling the non-volatile memory. The non-volatile memory has a pseudo pass function of returning a pass as a status even if a bit error reaching allowable number of bits occurs after at least one of a write or erase sequence is completed. The memory controller has an allowable bit change function of changing the upper limit value of the allowable number of bits.

Non-volatile memory system having a pseudo pass function

In order to avoid any malfunction for a temporary change in power supply voltage and suppress decrease in internal power supply voltage when transition is effected from the stand-by mode to the active mode, the disclosed semiconductor integrated circuit is provided with a detecting circuit which prevents malfunction in a temporary change in the power supply voltage from occurring by changing a detection level according to when the power supply voltage is increased or decreased. Further, a decrease in the internal power supply voltage immediately after the transition from the stand-by mode to the active mode is suppressed by employing a PMOS down converter in the stand-by mode and an NMOS down converter in the active mode, and setting an internal power supply voltage of the PMOS down converter in the stand-by mode higher than in the active mode. A down converter is formed in a lower layer of an external power supply line and peripheral circuit blocks are arranged in a lower layer of internal power supply lines on both sides of the external power supply line symmetrically with respect thereto, whereby a power supply distance of the power supply voltage is minimized and controllability of the internal power supply voltage is improved.

Semiconductor integrated circuit

Semiconductor integrated circuit with a down converter for generating an internal voltage

A memory cell array is divided into left and right cell arrays, each of which includes a plurality of blocks. Data erase is sequentially controlled by an erase control circuit on the basis of an erase command flag incorporated into a command register and an address incorporated into an address register. Batch erase is carried out with respect to selected blocks of the right and left cell arrays. After data erase, a verify operation is carried out with respect to the erased blocks by retrieving the erased blocks simultaneously with respect to the right and left cell arrays in parallel. Thus, the time required to retrieve the selected blocks for the verify operation after data erase is shortened, so that the time required to carry out the whole data erase is shortened.

Non-volatile semiconductor memory device and data erase controlling method for use therein

Semiconductor integrated circuit having active mode and standby mode converters

A memory incorporates a shield bit line reading system for fixing one of two bit lines disposed adjacent to each other to a shield potential and reading data to the other bit line. Selected bit lines are precharged to a power source potential, and then brought to a floating state. The shield bit lines are fixed to the power source potential. A period in which the power source potential is applied to the selected bit lines and a period in which the power source potential is applied to the shield bit lines are the same. A source line decoder applies the power source potential to sources of NAND cell units connected to selected bit lines and applies a ground potential to sources of NAND cell units connected to shield bit lines. Then, an output of data is produced from the memory cell to the selected bit lines.

Shielded bit line sensing scheme for nonvolatile semiconductor memory

The threshold voltage distribution for write operation into memory cells of a multi-level nonvolatile semiconductor memory device is precisely controlled and the verify result of written data is simultaneously detected for each page. For example, at the '10' data write time, excess write of '00' data which is a conventional problem is inhibited by controlling a path for transferring a lower bit to a bit line according to an upper bit. Further, at the write-verify time, the verify result can be simultaneously detected for each page by controlling the verify operation according to the upper bit. At the write time of '01' data, the bit line path is controlled by use of the lower bit and the write operation of '00' data is inhibited. Also, at the write-verify time, the verify result can be simultaneously detected for each page by controlling the verify operation according to the lower bit. The write and verify operations of '00' data can be effected in the same manner as in the case of '01' data by first inverting the lower bit of '00' data. Since the write operation can be effected while all of the write states of a plurality of bits are verified, each level of written data can be precisely controlled without causing excess or insufficiency in the threshold voltage after the write operation into the memory cell. Further, since the verify result can be simultaneously detected for each page, time can be significantly reduced.

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Kamakura, Japan

Yoshihisa Sugiura