Matsushita Electric Industrial Co., Ltd.

Matsushita Electronics Corporation

Panasonic Corporation

Other

Yoshihisa Nagano

Yasuhiro Uemoto

Eiji Fujii

Toru Nasu

Koji Arita

Akihiro Matsuda

Yasuhiro Shimada

Atsuo Inoue

Yuji Judai

Yasufumi Izutsu

Tatsuo Otsuki

Toshie Kutsunai

Taketoshi Matsuura

Takumi Mikawa

Shinichiro Hayashi

Masamichi Azuma

Toyoji Ito

Keisuke Tanaka

Akihiro Odagawa

Shoji Matsumoto

Keisaku Nakao

Hiroshige Hirano

Tatsumi Sumi

Satoshi Nakagawa

Hiroshi Yoshida

Tooru Nasu

Yoji Bito

Satoru Goto

Sadayuki Imanishi

Hajime Yasuoka

Eigi Fujii

An electro-resistance element that has a different configuration from conventional elements and is excellent in both affinity with semiconductor manufacturing processes and heat treatment stability under a hydrogen-containing atmosphere is provided. An electro-resistance element includes an electro-resistance layer that has two or more states in which electric resistance values are different and being switchable from one of the two or more states into another by applying a predetermined voltage or current. The electro-resistance layer includes first and second elements being capable of forming a nitride, and nitrogen.

Electro-resistance element and electro-resistance memory using the same

A protective insulating film is deposited over first and second field-effect transistors formed on a semiconductor substrate. A capacitor composed of a capacitor lower electrode, a capacitor insulating film composed of an insulating metal oxide film, and a capacitor upper electrode is formed on the protective insulating film. A first contact plug formed in the protective insulating film provides a direct connection between the capacitor lower electrode and an impurity diffusion layer of the first field-effect transistor. A second contact plug formed in the protective insulating film provides a direct connection between the capacitor upper electrode and an impurity diffusion layer of the second field-effect transistor.

Semiconductor device and method of fabricating the same

An electro-resistance element that has a different configuration from conventional elements and is excellent in both affinity with semiconductor manufacturing processes and resistance change characteristics is provided. An electro-resistance element has two or more states in which electric resistance values between a pair of electrodes and is switchable from one of the two or more states into another by applying a predetermined voltage or current between the electrodes. The electro-resistance element includes a substrate and a multilayer structure disposed on the substrate, the multilayer structure includes an upper electrode, a lower electrode and an electro-resistance layer disposed between the electrodes, wherein the electro-resistance layer includes FeO, and FeOcontained in an amount of 0% to 20% of FeOin percent by weight, the lower electrode is made of an iron oxide having a different composition from the electro-resistance layer and containing FeO, and the electro-resistance layer and the lower electrode make contact with each other.

Electro-resistance element, electro-resistance memory using the same and method of manufacturing the same

A method includes the steps of: forming a first insulation film on a substrate; forming a hole in the first insulation film; forming a lower electrode on a bottom surface and a sidewall surface of the hole; forming a capacitor insulation film on the lower electrode; forming a second conductive layer on the capacitor insulation film; forming a second insulation film on the second conductive layer so that the second insulation film fills a recess corresponding to the hole; forming a resist mask on the second insulation film so that the resist mask covers the recess; patterning the second insulation film by using the resist mask; and patterning the second conductive layer and the capacitor insulation film by using the patterned second insulation film as a hard mask. By dry etching using a hard mask, a dielectric capacitor having a three-dimensionally stacked structure can be formed with a high yield.

Method for manufacturing dielectric memory

The present invention provides a semiconductor device including a semiconductor element and a dummy semiconductor element adjacent to the semiconductor element. When the semiconductor element is a capacitor element including a bottom electrode, a top electrode and a dielectric layer between the electrodes, a dummy capacitor element also has dummy electrodes and a dummy dielectric layer between the dummy electrodes. The dummy electrode is located so that a space between the top electrode of the capacitor element ad the dummy top electrode is in a predetermined range (e.g. 0.3 &#x3bc;m to 14 &#x3bc;m). The dummy capacitor element prevents the capacitor dielectric layer from degrading since the collisions of the etching ions with the capacitor dielectric layer in a dry etching process is suppressed.

Semiconductor device having a ferroelectric TFT and a dummy element

A capacitor element is provided which is composed of a lower electrode, an upper electrode formed in opposing relation to the lower electrode, and a capacitor dielectric film made of a ferroelectric material or a high dielectric material and formed between the lower and upper electrodes. The lower electrode, the capacitor dielectric film, and the upper electrode are formed in a region extending at least from within a hole provided in an interlayer insulating film having a first hydrogen barrier film disposed on the upper surface thereof toward a position above the hole. A second hydrogen barrier film in contact with the first hydrogen barrier film is disposed to cover the upper surface of the upper electrode and the side surface of the portion of the upper electrode which has been formed above the hole.

Capacitor element

A semiconductor device includes: an insulating underlying layer of which surface portion has a concave portion; a lower electrode formed on the underlying layer along the inner face of the concave portion; a capacitor insulating film formed on the lower electrode and made of a high-dielectric or a ferroelectric subjected to thermal treatment for crystallization; and an upper electrode formed on the capacitor insulating film. The lower electrode and the upper electrode are made of a material that generates tensile stress in the thermal treatment for the capacitor insulating film, and the upper end part of the side wall and the corner part at the bottom face of the concave portion of the underlying layer are rounded.

Semiconductor device

A capacitormade up of a lower electrodea capacitive insulating filmof an insulating metal oxide and an upper electrodeis formed over a semiconductor substrateA first-layer wireis formed on a passivation filmthat covers the capacitorA first interlevel dielectric filmis deposited to cover the first-layer wireA second interlevel dielectric filmis deposited over the first interlevel dielectric filmwith a barrier filmwhich overlaps the capacitorfor preventing hydrogen from diffusing, interposed therebetween. A second-layer wireis formed on the second interlevel dielectric filmThe first interlevel dielectric filmhas a hydrogen content lower than that of the second interlevel dielectric film

Semiconductor device including a capacitor having a capacitive insulating film of an insulating metal oxide

A conductive oxygen barrier layer is formed on an interlayer dielectric film and patterned such that it is in contact with the top surface of a contact plug to prevent the diffusion of oxygen into the contact plug from above. The conductive oxygen barrier layer is composed of a lower layer containing a conductive nitride such as TiAlN, and an upper layer containing a conductive oxide such as IrO. An insulative oxygen barrier layer composed of AlOand having a thickness of approximately 20 nm is formed on the side surfaces of the conductive oxygen barrier layer to prevent the diffusion of oxygen into the contact plug from the sides, such as from the sides of the lower layer of the conductive barrier layer.

Semiconductor device and method for fabricating the same

A capacitive element includes a lower electrode having a three-dimensional shape, an upper electrode formed so as to be opposed to the lower electrode, and a capacitor insulating film formed between the lower and upper electrodes and made of a crystallized ferroelectric material. The thickness of the capacitor insulating film is set at 12.5 through 100 nm both inclusive.

Capacitive element and semiconductor memory device

A capacitor including a capacitor lower electrode, a capacitor dielectric film of a highly dielectric film or a ferroelectric film and a capacitor upper electrode is formed on a semiconductor substrate. A protection film is formed on the semiconductor substrate so as to cover the capacitor. A first TEOS film having a relatively large water content is formed on the protection film through first TEOS-OCVD where an ozone concentration is relatively low. A second TEOS-Ofilm having a relatively small water content is formed on the first TEOS-Ofilm through second TEOS-OCVD where the ozone concentration is relatively high.

Method of fabricating semiconductor device with capacitor covered by a TEOS-03 film

A semiconductor device includes: a capacitor provided on a supporting substrate having an integrated circuit thereon and including a lower electrode, a dielectric film, and an upper electrode; a first interlayer insulating film provided so as to cover the capacitor; a first interconnect selectively provided on the first interlayer insulating film and electrically connected to the integrated circuit and the capacitor through a first contact hole formed in the first interlayer insulating film; a second interlayer insulating film formed of ozone TEOS and provided so as to cover the first interconnect; a second interconnect selectively provided on the second interlayer insulating film and electrically connected to the first interconnect through a second contact hole formed in the second interlayer insulating film; and a passivation layer provided so as to cover the second interconnect.

A semiconductor memory device according to the present invention includes a memory cell capacitor for storing data thereon. The capacitor is made up of a first electrode connected to a contact plug, a second electrode and a capacitive insulating film interposed between the first and second electrodes. The first electrode includes a first barrier film in contact with the contact plug and a second barrier film, which is formed on the first barrier film and prevents the diffusion of oxygen. The second barrier film covers the upper and side faces of the first barrier film.

Semiconductor memory device

On a substrate, there are provided a lower electrode, a capacitance insulating film, a passivation insulating film, and a first partial film of an upper electrode to be filled in a second aperture (capacitance determining aperture) formed in the passivation insulating film. The lower electrode, the capacitance insulating film, and the first partial film constitute a capacitance element. The upper electrode has the first partial film which is in contact with the capacitance insulating film and a second partial film which is not in contact with the capacitance insulating film. Since a second electrode wire consisting of a lower-layer film composed of titanium and an upper-layer film composed of an aluminum alloy film is in contact with the second partial film distinct from the first partial film of the upper electrode, titanium or the like encroaching from the second electrode wire can be prevented from diffusing into the capacitance insulating film.

Growing community of inventors

Osaka, Japan

Yoshihisa Nagano