Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Other

Tokyo Shibaura Electric Co., Ltd.

Yoshihisa Mizutani

Yasushi Kawata

Hajime Yamaguchi

Takeshi Yamaguchi

Kohki Takatoh

Satoshi Shinozaki

Miki Mori

Yoshio Nishi

Naohiro Matsukawa

Koji Makita

Seizaburo Shimizu

Shinichiro Takasu

Susumu Kohyama

Syunzi Yokogawa

Minoru Kimura

The present invention of reflective liquid crystal display device include in: substrate having a surface; a pixel electrode on the surface; a first liquid crystal layer provided on the substrate; a second liquid crystal layer provided on the first liquid crystal layer; a counter electrode formed on the second liquid crystal layer; and a separating member provided between the first liquid crystal layer and the second liquid crystal layer. The first and second liquid crystal layers constituted by liquid crystal material having Bragg reflection(selective reflection in the same twist direction. The separating layer constituted optical compensator.

Reflective liquid crystal display device

A nonvolatile semiconductor memory device has n.sup.+ -type source and drain regions formed in the surface of a p-type semiconductor substrate, a floating gate formed above and insulated from a channel region provided between the source and drain regions, and a control gate formed above and insulated from the floating gate. The memory device further has a capacitor provided between the control gate and drain region.

Nonvolatile semiconductor memory device

Provided is a semiconductor device having a single continuous wiring layer in which a predetermined portion thereof is made of a semiconductor material, and the remaining portion thereof is made of a metal compound of the semiconductor material. The predetermined portion of the wiring layer preferably constitutes the gate electrode of a field effect transistor.

Semiconductor device with composite electrode

A memory cell structure for a non-volatile semiconductor memory has a semiconductor substrate and first and second diffusion layers having a conductivity type opposite to that of the substrate, formed on the substrate and serve as a source and a drain. The second diffusion layer is coupled through a contact hole to a conductive layer that serves as a bit line. The functions of the first and second diffusion layers as the source and drain are reversed between data write and read modes. A floating gate and a control gate are insulatively provided on the substrate in parallel to each other. In either the data write mode or data read mode, the first and second diffusion layer are applied with a bias voltage while the control gate is initially applied with a ground voltage. A memory cell is selected by dropping the bias voltage on the second diffusion layer. The potential on the first diffusion layer is kept unchanged to constantly maintain the initially-applied bias voltage even when the memory cell is selected, so that the first diffusion layer is permitted to be coupled to the common wiring line together with the corresponding first diffusion layers of the other memory cells.

Non-volatile semi-conductor memory device with double gate structure

An electrically erasable-programmable read-only memory device has memory cells formed on a semiconductive substrate. Each memory cell has source and drain layers, and a floating gate electrode and a control gate electrode insulatively provided above the substrate. First and second well regions having a polarity opposite to that of the substrate are formed therein so that each well region contains one or a plurality of memory cells therein. When information stored in the memory cell or memory cells in the first well region is to be rewritten with new information in a partial data rewrite mode, a potential of the first well region is independently controlled so as to inhibit reading and writing of information in the memory cells in the first well region. A potential of the second well region is separately controlled so as to allow writing of the new information in the memory cells in the second well region. The new information is written in the memory cell or memory cells in the second well region. The written information can be subjected to a following normal data read operation. The memory cell or memory cells in the first well region become inactive thereafter.

Semiconductor memory device

A semiconductor device, and more particularly, an erasable programmable read only memory has a control gate electrode and a floating gate electrode. The floating gate electrode is formed on one side wall of the control gate electrode through an insulating film.

EEPROM with sidewall control gate

A semiconductor device has P-type semiconductor body, a plurality of N-type wells formed in a surface area of the semiconductor body, and potential setting member for setting the potentials of the wells. This member has an N.sup.+ -type layer formed in the semiconductor body in contact with bottom surfaces of the wells, and an electrode formed on one of the wells.

Semiconductor device

An MOS transistor of second conductivity type is provided which is formed in a semiconductor substrate of first conductivity type and includes a first source region of second conductivity type, a first drain region of second conductivity type, and a gate electrode provided on a gate insulation layer. Further, an MOS transistor of first conductivity type is provided which is stacked on the MOS transistor of second conductivity type and includes a second source region, a second drain region and the gate electrode. The first and second source regions are connected to each other through a conductive layer which is selected from a given metal layer and a given metal silicide layer.

Stacked complementary metal oxide semiconductor inverter

A semiconductor memory device includes n.sup.+ -type first and second semiconductor regions which are separately formed in the surface area of a p-type semiconductor substrate, a floating gate and a control gate. The second semiconductor region acting as a drain in a data readout mode is composed of a main portion, and an additional portion having an impurity concentration lower than that of the main portion and formed in contact with the main portion and a channel region.

An electrically erasable and programmable read only memory comprises a semiconductor substrate of a first conductivity type, source and drain regions both of a second conductivity type formed in the surface of said semiconductor substrate, a gate insulation film formed on that section of the surface of said substrate which includes a channel region defined between said source and drain regions, a first diffusion region of the second conductivity type, part of which is formed in said substrate and contacts said drain region and which has a lower impurity concentration than said drain region, a first insulation film formed on said first diffusion region, a floating gate formed on said gate insulation film, part of which extends over said first insulation film, a second diffusion region of the first conductivity type formed in the surface of said first diffusion region which lies near said extension of the floating gate, a third diffusion region of the first conductivity type formed in the surface of said first diffusion region, a second insulation film covering said floating gate, and a control gate crossing at least that section of the surface of said second insulation layer which faces part of said floating gate.

Electrically erasable and programmable read only memory

A method for manufacturing a semiconductor device comprises a first step of forming a field insulation layer on a p-type semiconductor substrate and a second step of forming an n.sup.+ -type region and n-type region in an element area surrounded by the field insulation layer. In particular, the second step includes a step of forming, in the element area, a recess having an inclined portion and flat bottom portion, a step of forming an SiO.sub.2 film of a uniform thickness on the inclined portion and flat bottom portion, and a step of ion-implanting an n-type impurity into the substrate through the SiO.sub.2 and effecting an annealing process.

Method for manufacturing a recessed semiconductor device

A method of producing a semiconductor device comprises an isolation step for forming an n-type region in contact with p.sup.+ -type source and drain regions of a p-channel floating gate MOS transistor in the surface area of an n-type semiconductor substrate and an n.sup.+ -type region in contact with the n-type region. In this isolation step, and oxidation resistant film pattern is formed on the element region of the MOS transistor. An anisotropic etching is applied to the substrate with the oxidation resistant film pattern used as a mask to form an inclined portion and a flat portion, followed by forming a SiO.sub.2 film of a prescribed thickness to cover both the inclined and flat portions. Further, an n-type impurity is introduced by ion implantation into the substrate through the SiO.sub.2 film in a direction perpendicular to the flat portion, followed by annealing the ion-implanted region.

Method of producing semiconductor device

A metal-oxide-semiconductor device comprising source and drain regions formed in the surface region of a semiconductor substrate, and a gate electrode formed on an insulation layer on the channel region between the source and drain regions. The drain region includes an upper layer and a lower layer having an impurity concentration higher than that of the upper layer.

Metal-oxide-semiconductor device with bilayered source and drain

A method for fabricating a three-dimensional multi-layer integrated circuit of single crystalline CeO.sub.2 and Si is proposed. This method is characterized in that a single crystalline CeO.sub.2 insulation layer, or the like, is formed on a single crystalline Si substrate. An isolation region is formed in the single crystalline Si substrate. The region is transformed into a SiO.sub.2 insulation layer by selectively introducing oxygen ions through the single crystalline CeO.sub.2 insulation layer and reacting the oxygen ions with the single crystalline Si. An epitaxial growth single crystalline Si layer is formed on the single crystalline CeO.sub.2 insulation layer. Predetermined processes, such as forming a single crystalline CeO.sub.2 layer, are performed thereafter to form the three-dimensional structures of semiconductor elements such as MOS transistors and bipolar transistors with high packing density and reliability.

Method of fabricating three-dimensional semiconductor devices utilizing

Disclosed is a method of fabricating semi-conductor devices comprising the steps of: forming non-singlecrystalline semiconductor layer on a singlecrystalline insulation substrate, ion-implanting selectively material, which reacts with the semi-conductor layer to form insulating material, into the semiconductor layer; and applying an energy radiation or a heat treatment to the semiconductor layer, whereby the non-singlecrystalline semiconductor layer portion not implanted with said material is singlecrystallized with a seed of the singlecrystalline insulation substrate and at the same time the non-singlecrystalline semiconductor layer portion implanted with the material is rendered insulated.

Growing community of inventors

Tokyo, Japan

Yoshihisa Mizutani