Kabushiki Kaisha Toshiba

Yoshihisa Kondo

Kenji Sakaue

Takeshi Yoshida

Itaru Yamazaki

Junji Mori

Nobuhiro Ide

Masato Nagamatsu

Noboru Shibata

Takuya Futatsuyama

Hironori Uchikawa

Hitoshi Shiga

Tatsuyuki Ishikawa

Atsushi Takayama

Tarou Iwashiro

According to one embodiment, a memory system includes a memory cell array, first error correction part, second error correction part, and third error correction part. The memory cell array includes a first storage area in which 1-bit data is stored in one memory cell, and second storage area in which data of a plurality of bits is stored in one memory cell. When data is written to the first storage area, the first error correction part generates first parity data in the row direction on the basis of the data described above. The second error correction part corrects an error of the data described above on the basis of the first parity data read from the memory cell array. The third error correction part generates second parity data in the column direction on the basis of data of a plurality of pages.

Nonvolatile semiconductor memory system error correction capability of which is improved

A memory controller including a buffer configured to perform decoding frame-unit data decoded by an LDPC decoder through partial parallel processing based on a check matrix made up of a block of a unit matrix and a plurality of blocks in which each row of the unit matrix is sequentially shifted and store threshold decision information of the data read from a memory section, an LLR conversion section configured to convert the threshold decision information to an LLR, an LMEM configured to store probability information &#x3b2; calculated during iteration processing that repeatedly performs column processing and row processing based on the LLR in an iteration unit equal to or smaller than a size of the block, and a CPU core configured to transfer the probability information &#x3b2; stored in the LMEM to the buffer every time the iteration processing in the iteration unit is completed.

Memory controller, semiconductor memory apparatus and decoding method

A nonvolatile semiconductor memory system includes a semiconductor memory, at least one first error correction unit and at least one second error correction unit. The semiconductor memory stores a data frame encoded with LDPC codes. The at least one first error correction unit performs a first error correction for the data frame according to a first iterative decoding algorithm. The at least one second error correction unit performs a second error correction for the data frame which is failed to correct error by the at least one first error correction unit. The at least one second error correction unit performs the second error correction according to a second iterative decoding algorithm which uses a message having a larger number of quantization bits than that of the first iterative decoding algorithm.

Nonvolatile semiconductor memory system having first and second error correction units

A non-volatile semiconductor storage device according to an embodiment includes: a memory cell array including an array of electrically rewritable memory cells and configured to be able to store N bits of data (where N is a natural number not less than 2) in one memory cell; and a controller operative to control read, write and erase operations of the memory cell array. The memory cell array includes a first region having a first memory cell operative to retain N bits of data, and a second region having a second memory cell operative to retain M bits of data (where M is a natural number less than N). A data structure of address data received by the controller when accessing the first memory cell is the same as a data structure of address data received from the outside when accessing the second memory cell.

Non-volatile semiconductor storage device

A semiconductor storage device comprises: a sense amplifier circuit; a first data retaining circuit and a second data retaining circuit configured to retain data and threshold voltage information, the second data retaining circuit output the data and the threshold voltage information to the outside; and a control circuit configured to control operation. The sense amplifier circuit is configured to perform a data-read operation and a threshold-voltage-information read operation at the same time. The control circuit is configured to control read operations so that either one of the data or the threshold voltage information for which a read operation is finished earlier is output from the second data retaining circuit, and the other one of the data or the threshold voltage information for which a read operation is not finished yet is read from a memory cell array and retained in the first data retaining circuit.

Semiconductor storage device equipped with a sense amplifier for reading data and threshold-voltage-information data

A non-volatile semiconductor memory device has a memory core circuit including a cell array in which electrically rewritable and non-volatile memory cells are arranged therein, decoders configured to select the memory cells, and sense amplifiers configured to perform data read and write of the cell array, and a peripheral circuit including a memory controller configured to control data read and write in communication with the memory core circuit, wherein the memory controller has: an oscillator configured to generate an internal clock signal; a timing control circuit configured to timing control timings of data read and write of the cell array as synchronous with the internal clock signal; and a merge clock generation circuit configured to generate based on an external timing signal and the internal clock signal a merge clock signal serving for timing controlling a circuit portion in the peripheral circuit, the merge clock signal being defined as having a first signal period in which the external timing signal serves as a clock source and a second signal period without overlapping the first signal period, in which the internal clock signal serves as a clock source.

Non-volatile semiconductor memory device and electric device with the same

A logic circuit with a pipelined structure has a plurality stage of combinational circuits and memory circuits such as flip-flops connected among the pipeline combinational circuits. The pipeline combinational circuits constituting a logic circuit is operated at a cycle time shorter than a signal propagation time for the critical path of the pipeline combinational circuit. For the case of activation of the path not covered by this cycle time, another combinational circuit and its peripheral circuits are additionally provided for generating a correction signal. Another combinational circuit has substantially the same logic. The cycle time is determined so as to cover the critical path including another combinational circuit. A comparator circuit compares an output signal of another combinational circuit and an output signal of the combinational circuit. If both the signals are not coincident, a selector is controlled to correct the signal by using the output signal of another combinational circuit.

Logic circuit and method for designing the same

Disclosed is a pipeline information processing circuit which comprises a register control unit for outputting a plurality of data held in registers at a time; an arithmetic operation unit for carrying out a collective arithmetic operation of a plurality of data; and a bypass control unit for comparing an operation result outputted from the arithmetic operation unit and a data outputted from the register control unit, selecting a data to be an object of the next arithmetic operation, and transferring the selected data to the arithmetic operation unit through a suitable bypass.

Pipeline information processing circuit for floating point operations

A floating-point division cell consisting of partial remainder data register for storing parallel-partial-remainder data or third partial remainder data, divisor data register for storing parallel-divisor data or third divisor data, low-order divisor data generator for receiving the low-order portion of the divisor data and generating low-order divisor data, low-order partial remainder calculator for obtaining low-order multi-divisor data by multiplying the low-order divisor data and a multiple of 2 together and calculating new low-order partial remainder data by subtracting or adding the low-order multi-divisor data from/to the low-order portion of the partial remainder data, high-order divisor data generator for receiving the high-order portion of the divisor data and generating high-order divisor data, and high-order partial remainder calculator for obtaining high-order multi-divisor data by multiplying the high-order divisor data and a multiple of 2 together and calculating new high-order partial remainder data by subtracting or adding the high-order multi-divisor data from/to the high-order portion of the partial remainder data.

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Fujisawa, Japan

Yoshihisa Kondo