Toshiba Memory Corporation

Kioxia Corporation

Kabushiki Kaisha Toshiba

Fujitsu Corporation

Mitsubishi Jidosha Kogyo Kabushiki Kaisha

Mitsubishi Jidosha Engineering Kabushiki Kaisha

Toshiba Information Systems (japan) Corporation

Open-silicon Inc.

Toshiba Memory Coiporation

Yoshihisa Kojima

Riki Suzuki

Suguru Nishikawa

Takehiko Amaki

Toshikatsu Hida

Masanobu Shirakawa

Katsuhiko Ueki

Shunichi Igahara

Kiyotaka Iwasaki

Shohei Asami

Marie Takada

Tsukasa Tokutomi

Kazutaka Takizawa

Kazuya Kitsunai

Masaaki Niijima

Marie Grace Izabelle Angeles Sia

Hiroyuki Nemoto

Tatsuya Zettsu

Kiichi Tachi

Hiroyuki Moro

Tokumasa Hara

Mitsunori Tadokoro

Satoshi Arai

Tatsuhiro Suzumura

Yohei Hasegawa

Yoshiki Saito

Shunitsu Kohara

Shinichiro Nakazumi

Erika Kaku

Masami Aochi

Motohiro Matsuyama

Marie Sia

Nobuyuki Suzuki

Kengo Kurose

Ryo Yamaki

Takashi Ide

Norio Aoyama

Tohru Fukuda

Takaya Handa

Akinori Harasawa

Makoto Kuribara

Sumio Kuroda

Masahiro Kiyooka

Erika Ikeda

Shizuka Endo

Tomoya Kamata

Kazuaki Takeuchi

Takuya Futatsuyama

Hiroshi Sukegawa

Jawahar Jain

Hiroshi Yao

Kenichiro Yoshii

Hidekazu Suzuki

Hiroaki Yoshida

Akira Shimizu

Kouji Watanabe

Ikuo Magaki

Subramanian K Iyer

Debashis Sahoo

Yusuke Ochi

Amit Narayan

Kenichiro Suzuki

Takahiro Nango

Chihoko Shigeta

Nimish Rameshbhai Shah

Maoko Oyamada

Yuusuke Nosaka

Hironobu Miyamoto

Daisuke Mito

Purnabha Majumder

Balakrishna Kumthekar

John Mowchenko

Pramit Anikumar Chavda

Vamsi Boppana

Takaya Ogawa

Jialin Pan

According to one embodiment, there is provided a nonvolatile memory including a memory cell array, an input/output buffer, one or more intermediate buffers, and a control circuit. The memory cell array includes a plurality of pages. Each of the one or more intermediate buffers is electrically connected between the memory cell array and the input/output buffer. The control circuit is configured to store, in a first intermediate buffer, data read through sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers.

Nonvolatile memory including intermediate buffer and input/output buffer and memory system including the nonvolatile memory

According to one embodiment, a memory system includes a semiconductor memory, a controller, and a first circuit. The semiconductor memory includes a nonvolatile memory cell. The controller is configured to cause the semiconductor memory to execute first and second write operations. The first write operation writes a first bit into the memory cell. The second write operation writes first data based on the first bit and a second bit into the memory cell. The first circuit checks whether or not the first bit includes a bit error. The controller is configured to cause the semiconductor memory to execute, in the second write operation, writing of the first data including the second bit and a third bit obtained by correcting the bit error of the first bit, in a case that the first bit includes the bit error.

Memory system

According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.

According to one embodiment, a storage device comprises a nonvolatile memory, and a controller configured to perform a first data write operation in a first mode, and to perform a second data write operation in a second mode. Data of a first number of bits is written per memory cell in the first mode. Data of a second number of bits is written per memory cell in the second mode. The second number is larger than the first number. The controller reserves one or more free blocks as write destination block candidates of the first data write operation, perform the first data write operation for one of the write destination block candidates, and perform a garbage collection.

Storage device, storage system, and control method

According to one embodiment, a memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a first block that includes first and second sub-blocks. The memory controller instructs the non-volatile memory to execute a data erase process in units of sub-blocks on data stored in the non-volatile memory. In response to a first value corresponding to the first sub-block having reached a first threshold value, the memory controller reads first data from the first sub-block, executes an error correction process on the first data read from the first sub-block, and writes the first data on which the error correction process has been executed into the non-volatile memory.

A memory system includes a non-volatile memory chip that includes a memory cell array, and a memory controller. The memory controller is configured to perform a read operation on the non-volatile memory chip by instructing the non-volatile memory chip to perform a sensing operation to read data stored in the memory cell array, estimating a time when the read data becomes ready to be transferred from the non-volatile memory chip to the memory controller, and instructing the non-volatile memory chip, after the estimated time, to perform a transfer operation to transfer the read data to the memory controller.

Memory system including a non-volatile memory chip and method for controlling the non-volatile memory chip

According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.

According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.

Memory storage with selected performance mode

A memory system includes a memory device having a memory cell array, and a controller. The memory cell array includes a plurality of first units and at least one second unit. The second unit includes the plurality of first units. The controller counts a first number of times of read operation for each of the plurality of first units, and, in response to the first number of times for one first unit among the plurality of first units reaching a first value, updates a second number of times for the second unit that includes the one first unit. In response to the second number of times reaching a second value, the controller determines whether to rewrite data stored in at least one of the first units included in the second unit.

Memory system and method for managing number of read operations using two counters

According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to cause the nonvolatile memory to execute a first process of reading data based on a first request from a host device. The memory controller is configured to, when the first request is received from the host device while causing the nonvolatile memory to execute a second process, hold interruption of the second process until a first number becomes a first threshold value or more. The first number is a number of the first requests to be performed in the memory controller. The first threshold value is an integer of 2 or more.

A memory system includes a nonvolatile memory configured to execute one of a plurality of read operations, including a first read operation and a second read operation, and a memory controller configured to issue a read command to the nonvolatile memory to cause the nonvolatile memory to execute one of the plurality of read operations. The memory controller is configured to receive a read request, estimate a reliability level of a result of a read operation to be executed by the nonvolatile memory to read data from a physical address specified in the read request, select one of the first and second read operations to be executed first in a read sequence corresponding to the read request by the nonvolatile memory based on the estimated reliability level, and instruct the nonvolatile memory to execute the selected read operation.

Memory system, control method thereof, and program

According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes blocks each including memory cells. The memory controller is configured to control access to the nonvolatile memory. The memory controller is configured to: set a first block, among the plurality of blocks, to be written in a first mode, the first mode being a mode in which data of a first number of bits is written into the memory cell, and set a plurality of second blocks, among the plurality of blocks, to be written in a second mode, the second mode being a mode in which data of a second number of bits is written into the memory cell, the second number being larger than the first number; acquire access information related to the second blocks; and change a writing mode of the first block which has been set in the first mode to the second mode when a first condition of the second blocks based on the access information is satisfied.

Memory system and memory system control method

In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.

Memory system and controller

Growing community of inventors

Kawasaki, Japan

Yoshihisa Kojima