Canon Kabushiki Kaisha

Yoshihiro Terashima

Yukihiko Sakashita

Hiroshi Nonoshita

Nobuyuki Yuasa

To check operation of a circuit to be checked connected to a bus to which at least one master circuit and at least one slave circuit are connected, a model is connected to a bus in place of a master circuit or a slave circuit and cause given signals to be outputted at given timing for checking the operation of the circuit to be checked. Especially, by causing various data transfer to occur at random timing by a plurality of models, it is easy to cause severer than actual conditions to take place easily, enabling to enhance efficiency of checking. For example, when checking operation of a bus arbiter, a plurality of master models are connected in place of a plurality of master circuits to cause a request of bus accessibility to be outputted from each master model at random timing to check arbitration operation of a bus arbiter.

Method for logic checking to check operation of circuit to be connected to bus

To check operation of a circuit to be checked connected to a bus to which at least one master circuit and at least one slave circuit are connected, a model is connected to a bus in place of a master circuit or a slave circuit and cause given signals to be outputted at given timing for checking the operation of the circuit to be checked. Especially, by causing various data transfer to occur at random timing by a plurality of models, it is early to cause severer than actual conditions to take place easily, enabling to enhance efficiency of checking. For example, when checking operation of a bus arbiter, a plurality of master models are connected in place of a plurality of master circuits to cause a request of bus accessibility to be outputted from each master model at random timing to check arbitration operation of a bus arbiter.

A system can be realized by using a single frame memory, that is costly, to allow data write and data read operations continuously without suspending the video signal input. Such a memory controller comprises a serial/parallel converter section for converting serial input data into parallel data, an FIFO memory section for temporarily storing converted data, a memory section connected to the FIFO memory section to store data for a frame and a second FIFO memory section for temporarily storing the data read out from the frame memory section. The data bit width of said memory section is made equal to n times of the bit width of said input data so that data for a number of frames up to as many as (n-2) times of the number of input pixels can be read out of said memory section for said input data while the frequency of accessing said memory section can be reduced to a half or less than a half of the video signal input frequency.

Memory controller and liquid crystal display apparatus using the same

An image recording apparatus which realizes, at low cost, both an increased number of serially sensed frames and increased speed of serial image sensing. The image recording apparatus comprises: a photoelectric converter for converting light from an object to an electric signal; a first temporary storage for temporarily storing data outputted by the photoelectric converter; an image processor for performing image processing, including compression processing, on the data read out of the first temporary storage; a second temporary storage for temporarily storing the data, on which image processing has been performed by the image processor; and a recording device for recording the data, read out of the second temporary storage, in a recording medium.

Image recording apparatus, image recording method and storage medium

A memory controller comprises a first counter and a second counter, each having reset and enable functions, a vertical synch signal detector and a horizontal synch signal detector. A reset signal for the first counter is controlled by a signal detected by the vertical synch signal detector. An enable signal for the first counter and a reset signal for the second counter are controlled by a signal detected by the horizontal synch signal detector. An enable signal for the second counter is controlled in accordance with a signal indicating an image effective period. A memory address is controlled by the first and second counters.

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Kanagawa, Japan

Yoshihiro Terashima