Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Vlsi Limited

Transphorm Japan, Inc.

Socionext Inc.

Fujitsu Microelectronics Limited

Fujitsu Fanuc Limited

A. Aoki & Associates

Yoshihiro Takemae

Masao Nakano

Tomio Nakano

Kimiaki Sato

Masao Taguchi

Shigeki Nozaki

Hirohiko Mochizuki

Katsuhiko Kabashima

Yoshinori Okajima

Junji Ogawa

Hiroyoshi Tomita

Yasurou Matsuzaki

Makoto Yanagisawa

Seiji Enomoto

Nobumi Kodama

Atsushi Hatakeyama

Takaaki Suzuki

Yukinori Kodama

Tsuyoshi Ohira

Toshio Ogawa

Satoshi Eto

Makoto Koga

Hiroshi Yoshioka

Takashi Horii

Tsutomu Mezawa

Yoshiharu Kato

Fumio Baba

Takeo Tatematsu

Yasuro Matsuzaki

Hideaki Kawai

Tetsuhiko Endo

Yasuharu Sato

Takaaki Furuyama

Yasuhiro Fujii

Mitsuhiro Nagao

Masahiro Niimi

Hatsuo Miyahara

Norihisa Tsuge

Yukihiro Nomura

Tetsuhiko Endoh

Yasuharu Satoh

Naoharu Shinozaki

Koichi Nishimura

Kenichi Kawasaki

Hiroko Douchi

Tsutomu Hosoda

Yasuhiro Takada

Terumasa Kitahara

Norihisa Tsuge, Deceased

Hiroyuki Kobayashi

Toshiya Uchida

Masato Matsumiya

Yasushi Kasa

Yasuo Suzuki

Kotoku Sato

Tadao Aikawa

Toshiya Sato

Kiyoshi Miyasaka

Nobutaka Taniguchi

Shigemasa Ito

Makoto Niimi

Masanori Nagasawa

Eiichi Nagai

Gen Tsukishiro

Toyonobu Yamada

Katsumi Shigenobu

Ryuji Tanaka

Yuji Arayama

Tetsuya Endo

Toyomitsu Matsumoto

Sunao Araki

Masaaki Noguchi

Akira Terui

Masakazu Kanai

Satoshi Momozono

Sachie Tsuge

Itaru Tsuge

Takeo Takematsu

Yasumori Miyazaki

Masaru Satoh

Hirosuke Komyoji

Masaru Masuyama

Katsuhiko Itakura

A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

Memory system having a plurality of types of memory chips and a memory controller for controlling the memory chips

A driver circuit includes an output terminal connected to a gate of a Schottky transistor, a reference transistor formed in the same manner as the Schottky transistor, a resistor connected between a first power source line and a gate of the reference transistor, a voltage generator configured to supply a second node with a voltage equal to or lower than a voltage at a first node between the resistor and the reference transistor, and a switching element configured to transmit the voltage at the second node to the output terminal in response to a signal inputted to an input terminal.

Driver circuit of Schottky transistor

A semiconductor device, includes: a first field effect transistor having one terminal to which a first electrical potential is given; a second field effect transistor having one terminal to which a second electrical potential smaller than the first electrical potential is given; a controller that controls each electrical potential of each control terminal of the first field effect transistor and the second field effect transistor; a capacitor element having one end connected to the control terminal of the first field effect transistor, the capacitor element being charged by the control of the controller; and a load element connected between another terminal of the first field effect transistor and another terminal of the second field effect transistor.

Bootstrap circuit

A driving circuit of a schottky type transistor includes an input terminal supplied with an input signal, and an output terminal connected to a gate of the schottky type transistor. The driving circuit outputs a first voltage lower than a breakdown voltage of the schottky type transistor to the output terminal at the time of rising of the input signal, and thereafter supplies a second voltage higher than the breakdown voltage to a resistance connected to the output terminal.

Driving method and driving circuit of schottky type transistor

A switching circuit device has a first transistor which has a drain coupled to a high-potential terminal, a source coupled to a low-potential power supply, and, a driving circuit, which outputs, to a gate of the first transistor in response to an input control signal, a pulse having a potential higher than a threshold voltage of the first transistor and a potential of the low-potential power supply, wherein the driving circuit has a first inverter including a second transistor provided between the gate and the source of the first transistor, wherein when the first transistor changes from on to off due to the pulse, the second transistor conducts and short-circuits the gate and the source of the first transistor.

Switching circuit with controlled driver circuit

A transistor circuit includes a first high electron mobility transistor and a second high electron mobility transistor having a negative threshold voltage, wherein a source of the second high electron mobility transistor is coupled to a gate of the first high electron mobility transistor, and a gate of the second high electron mobility transistor is coupled to a source of the first high electron mobility transistor.

High electron mobility transistor circuit

A semiconductor device includes a first transistor including a GaN-based semiconductor stacked structure formed over a substrate, a first gate electrode having a plurality of first fingers over the semiconductor stacked structure, a plurality of first drain electrodes provided along the first fingers, and a plurality of first source electrodes provided along the first fingers; a second transistor including the semiconductor stacked structure, a second gate electrode having a plurality of second fingers over the semiconductor stacked structure, the second drain electrodes provided along the second fingers, and a plurality of second source electrodes provided along the second fingers; a drain pad provided over or under the first drain electrodes, and coupled to the first drain electrodes; a source pad provided over or under the second source electrodes, and coupled to the second source electrodes; and a common pad coupled to the first source electrodes and the second drain electrodes.

Semiconductor device and power supply apparatus

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Kasugai, Japan

Yoshihiro Takemae