Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Yoshihiro Takao

Shinji Sugatani

Daisuke Matsunaga

Koichi Hashimoto

Hikaru Kokura

Takayuki Wada

Katsumi Kakamu

Koichi Sugiyama

Tohru Fujita

Hiroshi Nomura

Satoshi Otsuka

Masaki Katsube

Kenichi Kanazawa

A semiconductor device includes a silicon substrate in which active regions of a memory cell are defined, a gate electrode formed on a device isolation insulating film to extend in a first direction, a first insulating film formed on the silicon substrate and the gate electrode, a first plug formed to penetrate the first insulating film, to overlap with the gate electrode and the first active region, and to extend in a second direction perpendicular to the first direction, a second plug penetrating the first insulating film above the second active region, a second insulating film formed on the first insulating film, and an interconnection buried in the second insulating film, and formed to recede from a side surface of the first plug in the second direction and to cover only part of an upper surface of the first plug.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a first transistor having a threshold voltage (Vth) adjusted to a first Vth by a first dopant having a first peak of concentration at a first depth; and a second transistor having the same channel-type as that of the first transistor and having a Vth adjusted to a second Vth by a second dopant having a second peak of concentration at a second depth equal to the first depth and higher concentration than the first dopant; wherein the first dopant and the second dopant are dopants comprising the same constituent element.

Semiconductor device having transistors

According to mask layout data created for a particular factory facility, transistors constituting a semiconductor device are classified into multiple groups depending on the gate length. Thereafter, the concentration of impurity introduced into a channel layer is set for each group, and thereby the gate length-threshold characteristics of a transistor are controlled. An overlapping area of a gate electrode and an element region of a certain group is extracted from mask layout data. The overlapping area is expanded to determine the shape of a mask used in injecting impurity in a channel layer. The data on the mask shape is then added to the mask layout data.

Method for creating mask layout data, apparatus for creating mask layout data, and method for manufacturing semiconductor device

A method of manufacturing a semiconductor device includes forming a first mask pattern exposing a first region for forming a first transistor and a second region for forming a second transistor, performing a first ion implantation for forming well regions using the first mask pattern, performing a second ion implantation for threshold voltage (Vth) adjustment of the first transistor using the first mask pattern, removing the first mask pattern and forming a second mask pattern in which the first region is covered and the second region is opened, performing a third ion implantation for Vth adjustment of the second transistor using the second mask pattern, forming first and second gate insulating films in the first and second regions respectively, and forming first and second gate electrodes in the first and second regions respectively.

Method of manufacturing a semiconductor device having transistors and semiconductor device having transistors

A semiconductor device includes a plurality of chips comprising a plurality of first moisture-proof rings individually surrounding said plurality of chips, a second moisture-proof ring surrounding the entire plurality of chips, and a wire for connecting said plurality of chips to each other.

The semiconductor device comprises a wellformed in a semiconductor substrateand having a channel region; a gate electrodeformed over the channel region with an insulating filminterposed therebetween; source/drain regionsformed in the wellon both sides of the gate electrode, sandwiching the channel region; and a pocket regionformed between the source/drain region and the channel region. The wellhas a first peak of an impurity concentration at a depth deeper than the pocket regionand shallower than the bottom of the source/drain regions, and a second peak of the impurity concentration at a depth near the bottom of the source/drain regions

Semiconductor device having well with peak impurity concentrations and method for fabricating the same

In each of a p-channel MOS transistor and an n-channel MOS transistor, a channel direction is set in the &#x3c;100&#x3e; direction and a first stressor film accumulating therein a tensile stress is formed in a STI device isolation structure. Further, a second stressor film accumulating therein a tensile stress is formed on a silicon substrate so as to cover the device isolation structure.

Semiconductor device and semiconductor integrated circuit device

The semiconductor device comprises a semiconductor substratewith a trenchand a trenchformed in; a device isolation filmburied in the trenchand including a liner film including a silicon nitride filmand an insulating filmof a silicon oxide-based insulating material; a device isolation filmburied in the bottom of the trench; and a capacitor formed on a side wall of an upper part of the second trenchand including an impurity diffused regionas a first electrode, a capacitor dielectric filmof a silicon oxide-based insulating film and a second electrode

Semiconductor device with shallow trench isolation which controls mechanical stresses

There are provided a gate electrode formed on a semiconductor substrate of one conductivity type via a gate insulating film, ion-implantation controlling films formed on both side surfaces of the gate electrode and having a space between the gate electrode and an upper surface of the semiconductor substrate, first and second impurity diffusion regions of opposite conductivity type formed in the semiconductor substrate on both sides of the gate electrode and serving as source/drain, a channel region of one conductivity type formed below the gate electrode between the first and second impurity diffusion regions of opposite conductivity type, and pocket regions of one conductivity type connected to end portions of the impurity diffusion regions of opposite conductivity type in the semiconductor substrate below the gate electrode and having an impurity concentration of one conductivity type higher than the channel region.

Semiconductor device and method of manufacturing the same

The semiconductor device comprises logic blocksforming a logic circuit, and interconnection regions. A gate interconnectionincluding the gate electrode of a load transistor Land the gate electrode of a driver transistor D, and the source/drain diffused layerof a load transistor Lare connected to each other by a conductor plug. A gate interconnectionincluding the gate electrode of a load transistor Land the gate electrode of a driver transistor D, and the source/drain diffused layerof the load transistor Lare connected to each other by a conductor plug. The source/drain diffused layerof a transfer transistor Tand the source/drain diffused layerof the first driver transistor Dare made common, and the source/drain diffused layerof the transfer transistor Tand the source/drain diffused layerof the driver transistor Dare made common. Accordingly, the area for the memory cells to be formed in can be made very small. The memory cells having such layout are used as the memory cells of the logic blocks and the switch matrices, whereby the areas for the logic blocks to be formed in and the switch matrices to be formed in can be made small. Thus, it is possible to contribute to down-sing, high integration and large capacity, etc. of semiconductor devices.

Semiconductor device

The semiconductor device comprises an interconnection buried in an interconnection groove formed in a lower insulating film, and an upper insulating film having a contact hole formed down to an end part of the interconnection. The interconnection groove is formed by using a design pattern having a main interconnection portionand an extended portionprovided at an end part of a main interconnection portionfor forming the interconnection and extended perpendicularly to an extending direction of the main interconnection portion

Semiconductor device including an electrical contact connected to an interconnection

A semiconductor device with p-channel MOS transistor having: a gate insulating film of nitrogen-containing silicon oxide; a gate electrode of boron-containing silicon; side wall spacers on side walls of the gate electrode, comprising silicon oxide; an interlayer insulating film having a planarized surface; a wiring trench and a contact via hole formed in the interlayer insulating film; a copper wiring pattern including an underlying barrier layer and an upper level copper region, and filled in the wiring trench; and a silicon carbide layer covering the copper wiring pattern. A semiconductor device has the transistor structure capable of suppressing NBTI deterioration.

Semiconductor device with copper wirings having improved negative bias temperature instability (NBTI)

Semiconductor device with copper wirings

Each of a plurality of repeating units comprises a plurality of memory cells. A second-conductivity-type well is formed in a surface layer of a semiconductor substrate extending over the plurality of the repeating units. In the second-conductivity-type well, first-conductivity-type channel MOS transistors of the plurality of the repeating units are provided. A second-conductivity-type well tap region is formed in one of the memory cells in each repeating unit and in the second-conductivity-type well. In the memory cell provided with the second-conductivity-type well tap region or in the memory cell adjacent thereto, an interlayer connection member is provided. The interlayer connection member is connected to the source region of one of the first-conductivity-type channel MOS transistors and to the corresponding second-conductivity-type well tap region.

Growing community of inventors

Kawasaki, Japan

Yoshihiro Takao