Fujitsu Corporation

Yoshihiro Mizushima

Kiyosumi Sato

Katsumi Ohnishi

Toshio Matsumoto

Motokazu Kato

Kazuyuki Shimizu

A data processing system comprising at least two operating systems (OS1, OS2) for virtual machines, a supervisory operating system, i.e., a control program (CP) for controlling the operating systems, control registers (CR0, CR1, ---) and an extended control register (ECR) having a special bit. When a control register operating instruction (LCTL or STCTL) is executed by one of the operating systems, the special bit has a first value and the operating system directly accesses the control register. When the other of the operating systems attempts to execute such a control register operating instruction, the special bit has a second value and an interruption is generated in the supervisory operating system.

System for directly and indirectly accessing control registers by

A pipeline control system for a computer in which predetermined tag data or micro instructions are stored in a plurality of tag registers while executing a first sequence of instructions in order to repetitively execute a flow of processing which is based upon the same. A required tag is selected from the tags stored in the tag registers in steps for executing second and subsequent sequences of instructions in which the same instructions can be repeated, so that the execution is initiated from a second phase without executing a first phase.

Pipeline control system for an execution section of a pipeline computer

This invention relates to a register and more specifically to register control in a data processing system. In general, a number of control registers are theoretically required that is less than the maximum number which can be designated, and only the required number of registers are mounted as hardware. In order to add functions or to provide compatibility with other systems, it is sometimes required to use a register that is not mounted as hardware, or to use the registers mounted as hardware for conflicting purposes. Virtual registers are accordingly provided for at address locations in the memory of the processing system. However, if only the registers to be added are thusly provided for in the memory, the instructions must be executed by distinguishing between register access and memory access, in accordance with register number, etc. Thus, this invention provides a number of virtual registers for instance equal to the number that can be designated. The controls are thereby simplified in accordance with the kind of instruction to be performed. Namely, when an instruction is the LOAD instruction, the same content is loaded into both real an virtual registers from a respective address of the memory, and when it is the STORE instruction, the content from a respective virtual register is stored into the respective address of the memory.

Register control processing system

A machine check processing system which includes: an error correcting circuit for correcting a correctable error generated during data processing; an error data storage for storing error data which relates to the correctable error; a central processing unit (CPU) for controlling the error correcting circuit and the error data storage; and a service processing unit (SVP) for operating and controlling the error correcting circuit, the error data storage, and the CPU. The CPU includes an error data freezing circuit for freezing error data stored in the error data storage when a correctable error occurs, and a machine check record request signal generator for generating a machine check record request signal when a correctable error occurs. The SVP comprises an error data saving device for carrying out a saving process to save the frozen error data stored in the error data storage in response to the machine check record request signal, an error data analyzing circuit for carrying out an error analyzing process and a freeze release circuit for releasing the error data stored in the error data storage from a frozen state after the error data saving device saves the error data. At least a part of the saving process and the error analyzing process are automatically carried out substantially simultaneously with the operation of the CPU, without a machine check interruption.

Machine check processing system

This invention relates to a timing control, for example, a control for reserving a waiting time when a data processor sends or receives data to or from an external device. Dummy cycles for a number of cycles having a processing time equal to the desired waiting time are generated by a dummy instruction. A timing control system is disclosed which is especially suitable for a micro-program system of a pipeline control system.

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Kawasaki, Japan

Yoshihiro Mizushima