Hitachi, Ltd.

Hitachi Process Computer Engineering, Inc.

Hitachi Engineering Co., Ltd.

Hitachi Information Control Systems, Inc.

Arix Computer

Yoshihiro Miyazaki

Shinichiro Yamaguchi

Soichi Takaya

Tadaaki Bandoh

Jushi Ide

Hidekazu Matsumoto

Yoshiaki Takahashi

Kenichi Kurosawa

Tetsuaki Nakamikawa

Shin Kokura

Masayuki Tanji

Hiroaki Fukumaru

Manabu Araoka

Naoto Miyazaki

Masayuki Sakata

Koji Matsuda

Tomoaki Nakamura

Atsuhiko Nishikawa

Hiroaki Nakanishi

Takayuki Morioka

Hirokazu Hirayama

Yukio Kawamoto

Yuuichiro Morita

Atsushi Shikama

Nobuo Akeura

Takeshi Kato

Akira Yamagiwa

Masahiko Saito

Hiroshi Kuwahara

Daniel M McCarthy

Shigenori Kaneko

Kenji Kashiwagi

Hidehito Takewa

Masao Inoue

Kenkichi Yamashita

Hisao Ogawa

Atomi Noguchi

Koji Masui

Takao Kobayashi

Ryosei Hiraoka

Sako Ishikawa

Syoji Yamaguchi

Hiroshi Ohguro

Satoru Kayukawa

Kenzi Hirose

Morioka Takayuki

Siochi Takaya

Kazuhiro Hyuga

Masataka Hiramatsu

Hiroshi Oguro

A multiplexed computer system allows memory accessing by a processor, a peripheral equipment or a like apparatus even during execution of memory copying to improve the processing performance during on-line maintenance. To this end, the multiplexed computer system includes a plurality of processing units which effect the same operation in synchronism with each other. Each of the processing units includes a copy processor register for designating a processor to read out contents of a memory unit, a memory copy control unit for transferring copies of the stored contents of the memory unit and data to be written into the memory unit in the same order as that of accesses to the memory unit of the other processing unit, a copy mode flag indicating that memory copy processing for making the stored contents of the memory unit of the self system and stored contents of the memory unit of the other processing unit coincide with each other is proceeding, and a copy task flag indicating that the processor is reading out, during memory copying processing, the stored contents of the memory unit.

Multiplexed computer system

A computer and a backup computer exchange periodic report signal transmissions by way of SVP115. When there is no periodic report signal transmission from the main computer, the backup computer makes a main computer status inquiry and if one location is malfunctioning resets the main computer by way of the SVP115 and continues the processing. When permanent damage is present, the SVP115 continually resets the main computer and controls MOS switches of the common disk unit to isolate the SCSI from the main computer and continue the main computer processing.

Common disk unit multi-computer system

A fault-tolerant computer system, which prevents an I/O fault from reaching the CPU block while using an alternative I/O block to continue processing, employs common general-purpose processors with a minimum of specialized peripheral circuits. Dual system bus adapters are provided not in the fast-operating CPU portion requiring sophisticated packaging technology, but in the low-speed interface between the CPUs and the I/O bus adapters. This allows the CPUs and I/O bus adapters to be shared by ordinary data processors, workstations, or personal computers while implementing a fault-tolerant computer system. If a one-shot hardware fault occurs in a CPU or in an I/O bus adapter, the faulty component is disconnected from the system so that the system will operate uninterruptedly.

Fault-tolerant computer system

A multiplexed computer system allows memory accessing by a processor, a peripheral equipment or a like apparatus even during execution of memory copying to improve the processing performance during on-line maintenance. To this end, the multiplexed computer system includes a plurality of processing units which carry out the same operation in synchronism with each other. Each of the processing units includes a copy processor register for designating a processor to read out contents of a memory unit, copying circuits which transfer copies of the stored contents of the memory unit and data to be written into the memory unit in the same order as that of accesses to the memory unit to a memory unit of another processing unit, a copy mode flag indicating that memory copying processing for making the stored contents of the memory unit of the self system and stored contents of the memory unit of the other processing unit coincide with each other is proceeding, and a copy task flag indicating that the processor is reading out, during memory copying processing, the stored contents of the memory unit.

Multiplexed computer system with the capability to copy data from one

The present invention concerns clock source switchover between dual clock sources in the event of failure of any of them without affecting the clock output in the dual system, thereby preventing malfunctioning of processors therein. In the fault tolerant computer system of the invention, each of the plural processing units comprises a clock source, a clock selector, a clock stop detection unit, a clock phase adjusting unit, and a phase coincidence detection/operation suppression/resetting unit, whereby when switching over from a faulty clock source to a normal clock source in the event of clock failure, the clock phase adjusting unit ensures continuity in the output clock signals. The clock phase adjusting unit provided in the subsequent stage of the clock selector inserts the PLL circuit having an overdamping response characteristic obtained by lowering the gain of its loop filter.

Uninterruptible clock supply apparatus for fault tolerant computer system

A dual computer system consisting of two computer systems connected by a plurality of data transfer units and a plurality of data transfer channels for a memory copy made to again synchronize both the computer systems at the time of recovery from a fault. When no fault occurs on the data transfer channels, the data transfer units share the load of data transfer in the memory copy operation, and when a fault occurs on any data transfer unit during the memory copy operation, the remaining normal data transfer units are used to again transfer data, whereby a memory copy is made at high speed for again synchronizing both the computer systems at the time of recovery from a fault, and system reliability at the time of recovery from a fault is improved.

Dual information processing system having a plurality of data transfer

A method of verifying operation concurrence in maintenance/replacement of twin CPUs employed in a dual-CPU computer wherein a replacement CPU with an initial fault may have been installed by mistake during on-line maintenance/replacement work and a system therefor are disclosed whereby a failure which, without the method and the system, would occur due to the initial fault of the replacement CPU during a dual subsystem synchronous operation carried out thereafter by the computer can be prevented from entailing a system down on both the subsystems.

Method of and system for verifying operation concurrence in

A multiple common memory system is provided in which at least three CPUs share at least two common memories each storing one and the same content. Each of the first and second CPUs contains a respective one of the two common memories, and each of the first and second CPUs has an arrangement to access the common memory therein at the time of requesting a read access to a common memory. Other CPUs in the system do not contain common memories, but do include arrangements to access the common memory of the first or second CPU at the time of requesting a read access to a common memory.

Method for controlling multiple common memories and multiple common

In a data processing device, when exchanging a plug-in package with another without breaking the power to be supplied to the data processing device, a package removing lever is equipped with a locking piece. The lever does not move and the package hence cannot be removed, until the locking piece is released. In response to the release operation of the locking piece, a switch is activated to break off the power supply for the package. After the package is mounted perfectly, the power for the package is switched on by the action of the locking piece, thus preventing any misoperation when removing the package.

Data processing device and plug-in package

A method and apparatus for controlling a dual bus system, capable of realizing high speed and continuous operation even if one of the buses of the dual bus system fails. The method and apparatus has a dual bus system, a plurality of electronic circuits connected to both buses of the dual bus system, and bus controller for providing a bus use allowance signal to one of the plurality of electronic circuits, the one electronic circuit being selected in accordance with bus occupation request signals issued from the plurality of electronic circuits requesting data transfer. If the bus occupation request signals for both buses of the dual bus system originates from the one selected electronic circuit and the outputs of the arbiters coincide, the bus use allowance signal is provided to the one selected electronic circuit for the allowance of occupying both buses of the dual bus system. A completion of data transfer at the dual bus system is determined when data transfer is completed at both buses. Continuous operation can be ensured immediately upon occurrence of a failure, and high speed operation of a computer system is possible.

Method and apparatus for controlling dual bus system

In a data processing device, when exchanging a plug-in package with another without breaking off the power to be supplied to the data processing device, a package removing lever is equipped with a locking piece. The lever does not move and the package hence cannot be removed, until the locking piece is released. In response to the release operation of the locking piece, a switch is activated to break off the power supply for the package. After the package is mounted perfectly, the power for the package is switched on by the action of the locking piece, thus preventing any misoperation when removing the package.

A data processing device which includes a common memory connecting mechanism which is located between a memory bus to which copyback cache is connected, and a common memory. The common memory connecting mechanism includes a slave type transfer mechanism which directly assesses the common memory bypassing the cache and processes thereof, and a data mover which transfers data between the common memory and main memory.

Data processing device with common memory connecting mechanism

Method and apparatus for instruction restart processing in a microprogram-controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.

System for storing restart address of microprogram, determining the

A co-processor control method intended to speed up data transfer linkage between the co-processor and memory when the co-processor is activated by the main processor, in such a way that the main processor issues an active control signal to the co-processor in the cycle of reading out an operand in the memory onto the data bus by being addressed by the main processor so that the operand on the data bus is directly delivered to the co-processor.

Method for fast establishing a co-processor to memory linkage by main

Method and apparatus for instruction restart processing in a microprogram - controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.

Suspended instruction restart processing system based on a checkpoint

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Hitachi, Japan

Yoshihiro Miyazaki