Kabushiki Kaisha Toshiba

Other

Yoshihiro Minami

Takashi Yamada

Hajime Nagano

Naoto Miyashita

Tsutomu Sato

Takeshi Hamamoto

Kazumi Inoh

Takashi Ohsawa

Takashi Shinohe

Ichiro Mizushima

Ichiro Omura

Shinji Sato

Tsuneo Ogura

Yusuke Kohyama

Hiroyuki Kanaya

Ryo Fukuda

Yukiteru Matsui

Akihiro Nitayama

Tatsuya Ohguro

Shinji Miyano

Hiroaki Yamada

Hisato Oyamatsu

Shigeru Kawanaka

Yoshikuni Tateyama

Osamu Fujii

Tomoaki Shino

Kenji Kojima

Jun Takayasu

Shinichi Nitta

Takeo Kubota

Yasuhiro Katsumata

Shigeru Hasegawa

Hiroshi Kato

Atsushi Azuma

Kazuhiko Hayashi

Kenji Doi

Hiroyuki Kohno

Hiroshi Takenaka

A memory includes memory cells on a semiconductor layer, in which each of the memory cells includes a source layer and a drain layer in the semiconductor layer; an electrically floating body region provided in the semiconductor layer between the source layer and the drain layer and configured to accumulate or discharge electric charges in order to store logical data; a gate dielectric film provided on the body region and comprising a ferroelectric film with polarization characteristics; and a gate electrode provided on the gate dielectric film above the body region, wherein each memory cell stores a plurality of logical data depending on an amount of electric charges accumulated in the body region and on a polarization state of the ferroelectric film.

Semiconductor memory device

This disclosure concerns a semiconductor memory device including bit lines; word lines; semiconductor layers arranged to correspond to crosspoints of the bit lines and the word lines; bit line contacts connecting between a first surface region and the bit lines, the first surface region being a part of a surface region of the semiconductor layers directed to the word lines and the bit lines; and a word-line insulating film formed on a second surface region adjacent to the first surface region, the second surface region being a part of out of the surface region, the word-line insulating film electrically insulating the semiconductor layer and the word line, wherein the semiconductor layer, the word line and the word-line insulating film form a capacitor, and when a potential difference is given between the word line and the bit line, the word-line insulating film is broken in order to store data.

A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains.

Semiconductor memory device and manufacturing method thereof

A first electrode film, a ferroelectric film, and a second electrode film are accumulated above a semiconductor in this order, a hard mask is accumulated above the second electrode, scrub cleaning is performed on the surface of the hard mask with an surfactant, the hard mask on which the scrub cleaning is performed has been patterned according to a planar shape of a ferroelectric capacitor, and etching is performed by using as a hard mask the hard mask that has been patterned.

Fabricating method of nonvolatile semiconductor storage apparatus

A semiconductor memory device includes: a semiconductor device base having an insulating substrate and a semiconductor layer overlying it; a cell array formed on the semiconductor device base with cell transistors disposed in such a manner that each of source and drain layers is shared by adjacent two cell transistors arranged in a direction, the cell transistor having an electrically floating channel body to store data defined by a carrier accumulation state of the channel body; and logic transistors formed on the semiconductor device base to constitute a peripheral circuit of said cell array, wherein at least a part of source and drain layers of each the cell transistor is formed with a thickness different from source and drain layers of the logic transistors.

Semiconductor memory device with cell transistors having electrically floating channel bodies to store data

A semiconductor device comprises a semiconductor substrate; an embedded insulating layer provided on the semiconductor substrate; a semiconductor layer provided on the embedded insulating layer; a transistor including a first conductivity type source layer formed within the semiconductor layer, a first conductivity type drain layer formed in the semiconductor layer, and a channel forming region between the source layer and the drain layer; and an embedded insulating layer protective diode including a second conductivity type first diffusion layer and a first conductivity type second diffusion layer, the first diffusion layer being at the same potential as a semiconductor substrate region immediately below the channel forming region, the second diffusion layer being provided adjacently to the first diffusion layer and electrically connected to at least one of the source layer, the drain layer and the channel forming region.

Semiconductor device

A hollow region is formed in a silicon substrate. A plurality of openings formed in the silicon layer on the hollow region is filled with a buried film. The bottom portion of the hollow region is formed with a plurality of silicon pillars, which support the silicon layer.

Semiconductor device having a hollow region and method of manufacturing the same

A spiral inductor comprising: a substrate; a protruding portion which is formed on the top face of the substrate and the top of which serves as a dummy element for controlling a chemical mechanical polishing process; and a conductive layer which is formed on the substrate so as to have a spiral shape and which serves as an induction element, wherein the protruding portion is formed in a region other than a region directly below the conductive layer.

Semiconductor device with spiral inductor and method for fabricating semiconductor integrated circuit device

A convex polycrystalline silicon film is formed on a handle wafer. A semiconductor layer is formed on the polycrystalline silicon film. The semiconductor is thinner on its areas in which the convex polycrystalline silicon film is formed and is thicker on its areas in which the convex polycrystalline silicon film is not formed. An opening is formed in each of those areas of an insulating film which are located under respective thick-film semiconductor areas of the semiconductor layer. The polycrystalline silicon film is formed in the openings to connect electrically the thick-film semiconductor areas and the handle wafer together.

Semiconductor device comprising plurality of semiconductor areas having the same top surface and different film thicknesses and manufacturing method for the same

A semiconductor device includes first and second semiconductor layers and first and second MOS transistors. The first semiconductor layer is provided on and electrically connected to the semiconductor substrate. The second semiconductor layer is provided near the first semiconductor layer and formed above the semiconductor substrate via one of an insulating film and a cavity. The first and second MOS transistors are respectively provided on the first and second semiconductor layers, and each has a gate electrode arranged parallel to a boundary between the first and second semiconductor layers.

Semiconductor device having one of patterned SOI and SON structure

A dresser is used which makes it possible to simultaneously dress and condition the surface of a polishing pad deteriorated by polishing a semiconductor wafer in the CMP process. The dresser is a dresser comprised of a ceramic such as dressing SiC, SiN, alumina or silica. Use of this dresser enables to shorten the time of dressing/conditioning the deteriorated polishing pad.

Method for dressing a polishing pad, polishing apparatus, and method for manufacturing a semiconductor apparatus

A semiconductor device comprises: a semiconductor substrate; an insulating layer provided on said semiconductor substrate; a first semiconductor layer provided on said insulating layer; a plurality of openings penetrating said first semiconductor layer and said insulating layer and reaching said semiconductor substrate; and second semiconductor layers filling said openings by selective growth and connected to said semiconductor substrate, wherein areal sizes of said plurality of openings are substantially equal to each other.

A semiconductor wafer or a film formed thereon is polished by using a polishing agent comprising abrasive containing silica particles as the main component, water as a solvent, and a water-soluble cellulose, an alkali metal impurity content of the polishing agent being 5C ppm or less where the polishing agent contains C % by weight of the water-soluble cellulose, so as to flatten the semiconductor wafer without doing damage to the wafer or the film formed thereon and without bringing about a dishing problem in the polished surface.

Growing community of inventors

Fujisawa, Japan

Yoshihiro Minami