Fujitsu Corporation

Fuji Furukawa Engineering & Construction Co., Ltd

Yoshihiro Kusano

Naoki Shinjo

Hideki Kimura

Yoichi Sato

Akihiro Yasuo

Katsuhiko Nakata

Hitoshi Nori

Mitsuo Hayashi

Yoshihisa Iwakiri

Kengo Ueda

Tomoaki Haneda

Kenji Tosaka

Mika Tokumitsu

Kouji Kuroda

Tsutomu Tanaka

Hiroshi Murakami

Takao Kato

Masayuki Ikeda

Haruhiko Ueno

Hideki Sakata

Satoshi Nakagawa

Yoshinori Sugisaki

Gou Sugizaki

Akitoshi Ino

Shin Okada

To cool a blade type server disposed in an air-conditioned room, the following arrangements are made. The first is at least one shell having a ventilation passage disposed in the air-conditioned room. The second is, the following are disposed in a ventilation passage: racks, in which blade type servers each composed of a case with slim boards housed therein are stacked; cooling coils each having a coolant passage and a cooling fin and cooling a passing air; and at least one fan unit having axial-flow fans placed therein and producing air currents in one direction. The third is the fan unit forces a cooling air to flow in one direction in the ventilation passage thereby to cool the servers in the racks. The cooling coils and racks are disposed alternately so that warmed cooling air after passing through the rack is cooled by the cooling coil and then cools the next rack.

Cooling system for information device

A plurality of system board modules are connected to a crossbar module. An error detection unit detects an error in a packet received from a corresponding system board module. When an error is detected by the error detection unit, a transmission control unit issues a completion data generation request. When receiving the completion data generation request, a packet completion unit generates completion data. When receiving an error packet, a selector circuit outputs a completion packet in which completion data is provided in place of a data unit involving error.

Interconnection device

A parallel computer of a distributed storage type, which can omit an overhead time of a processing apparatus required for an address computation, is provided with an array address converting apparatus for generating a PE number of a PE retaining an array element that is an object of an access and an address on storage apparatus of the array element within the PE in each PE. Upon an access to an array element of array data, the processing apparatus activates the array address converting apparatus, a communicating apparatus gives an address on storage apparatus generated by the array address converting apparatus to a PE having a PE number generated by the array address converting apparatus to transmit access demand information for the array element. This parallel computer of a distributed storage type is applicable to a computer system for processing enormous data at a high speed such as numerical calculation, image processing or the like.

Parallel computer of a distributed storage type

A dynamic address translation processing apparatus in a data processing system having a main memory for storing an address conversion table, and a central processing unit for converting a virtual address to a real address by referring the address conversion table. The central processing unit includes a first register for holding the virtual address, a second register for holding a table entry of the address conversion table corresponding to the virtual address held in the first register and, having an update bit indicative that a page in memory has been written to a third register for holding the real address of the table entry held in the second register, a comparison circuit for comparing the virtual address held in the first register with the other virtual address to be converted to the real address, and an update unit for updating the update bit in the table entry held in the second register. When the virtual address coincides with the other virtual address in the comparison circuit, the table entry converted by the update unit is written into an address of the main memory held in the third register.

Dynamic address translation allowing quick update of the change bit

A data processing device having a CPU and a memory device includes a unit for temporarily storing information concerning a predicted access which is expected to occur subsequent to the occurrence of an access. The unit is searched to obtain a predicted access address, which is activated in advance, so that data can be efficiently pre-fetched.

Data pre-fetch control device

Growing community of inventors

Kawasaki, Japan

Yoshihiro Kusano