Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Socionext Inc.

Yoshihiro Koga

Kensuke Odani

Manabu Kuroda

Kiyohiko Sumida

Takaharu Morohashi

Tetsuya Tanaka

Takeshi Tanaka

Shuji Miyasaka

Tokuzo Kiyohara

Masato Suzuki

Taketo Heishi

Hideshi Nishida

Hajime Ogawa

Michihiro Matsumoto

Kouji Nakajima

Hazuki Okabayashi

Kazutoshi Funahashi

Teruyuki Morita

Noboru Asai

Masakazu Fujimoto

A computer system includes: a main storage unit, a processing executing unit sequentially executing processing to be executed on virtual processors; a level-1 cache memory shared among the virtual processors; a level-2 cache memory including storage areas partitioned based on the number of the virtual processors, the storage areas each (i) corresponding to one of the virtual processors and (ii) holding the data to be used by the corresponding one of the virtual processors; a context memory holding a context item corresponding to the virtual processor; a virtual processor control unit saving and restoring a context item of one of the virtual processors; a level-1 cache control unit; and a level-2 cache control unit.

Multi-threaded processor context switching with multi-level cache

A media processing method for performing media processing by causing a processor to execute plural program modules, includes controlling input/output of media data, determining at least one call time, and calling a second program module in a second layer at each determined call time, by executing a first program module in a first layer, the first layer being higher than the second layer. The method further includes causing the processor to perform data conversion on the media data, by executing the second program module in the second layer, the data conversion being part of the media processing.

Media processing method and media processing program

A media processing method for performing media processing by causing a processor to execute plural program modules, including: a first step of controlling input/output of media data, determining at least one call time, and calling a second program module in a second layer at each determined call time, by executing a first program module in a first layer, the first layer being higher than the second layer; a second step of calling at least one third program module in a third layer, the third layer being lower than the second layer, by executing the second program module in the second layer; and a third step of causing the processor to perform data conversion on the media data, the data conversion being an element of the media processing, by executing the third program module in the third layer.

A semiconductor device has a processor, a first memory unit accessed by the processor, a plurality of page memory units obtained by partitioning a second memory unit which is accessible by the processor at a speed higher than the speed at which the first memory unit is accessible such that each of the page memory units has a storage capacity larger than the memory capacity of a line composing a cache memory, a tag adding, to each of the page memory units, tag information indicative of an address value in the first memory unit and priority information indicative of a replacement priority, a tag comparator for comparing, upon receipt of an access request from the processor, the address value in the first memory unit with the tag information held by the tag, and a replacement control unit for replacing the respective contents of the page memory units.

Memory replacement mechanism in semiconductor device

A processor according to the present invention includes a decoding unit, an operation unit and others. When the decoding unit decodes an instruction 'vxaddh Rc, Ra, Rb', an arithmetic and logic/comparison operation unit and others (i) adds the higher 16 bits of a register Ra to the lower 16 bits of the register Rb, stores the result in the higher 16 bits of a register Rc, and in parallel with this, (ii) adds the lower 16 bits of the register Ra to the higher 16 bits of the register Rb, and stores the result in the lower 16 bits of the register Rc.

Processor executing SIMD instructions

A variable length decoding device comprising:

Variable length decoding device and variable length decoding method and reproducing system

In order to enable a pointer register device including registers called shadow registers to conduct updating operation rapidly by arithmetic operation of a pointer value between the registers, a front/back register set includes a first register and a second register. A switch control section allows a read select switch and a write select switch to select different registers. When the read select switch selects the first register and the write select switch selects the second register, the sum obtained by an adder can be stored in the second register while retaining the pointer value of the first register. In this case, the pointer value need not be transferred between the registers.

Device and method for updating a pointer value by switching between pointer values

Growing community of inventors

Osaka, Japan

Yoshihiro Koga