Kawasaki Steel Corporation

Kawasaki Microelectronics, Inc.

Sony Corporation

Yoshihiro Ishida

Masato Yoneda

Hiroshi Yoshizawa

Tomohiro Marui

Hideo Nakano

Hiroyuki Oka

Masatoshi Takashima

Daisuke Hiranaka

Keisuke Aoki

Masahiro Konishi

Hideyuki Narita

Izumi Hayashibara

Hirofumi Morimoto

Yoshinori Wakimoto

An image processing apparatus that includes an image acquiring unit that acquires a plurality of images, a processing unit that creates a plurality of composite images having a sequential relationship based on a predetermined rule using at least a portion of each of the acquired images, and selects a representative image corresponding to the plurality of composite images.

Imaging device, display control method and program

The configuration of a CAM device can be set in various manners depending on a system in which CAM having different configurations is needed. The CAM device includes a CAM array including a plurality of physical banks, a logical bank-physical bank converter for setting the assignment between logical banks and physical banks, and for outputting a control signal to set the configuration of a physical bank assigned to the logical bank, depending on a logical bank signal indicating a logical bank to be searched, a priority circuit for outputting search results in accordance with predetermined priority, and a cascade circuit for performing a logical operation on the search results output from the priority circuit of the present CAM device and a search results supplied from a higher-order CAM device, and transmitting the results of the logical operation to a lower-order CAM device.

Content addressable memory device capable of being used in cascaded fashion

A data transmission method able to maintain the quality of a transmitted image substantially same as that of one's own image and an apparatus using the method and a data transmission system, transmitting image data accommodated in a frame of a preset frame during communication between terminals, comprising capturing an image including a target image to be transmitted, making adjustments so that the target image to be transmitted from the obtained image substantially fully fills the image frame, and compressing and transmitting the adjusted image data in the image frame.

Data transmission method, apparatus using same, and data transmission system

In a binary search, two storage units are prepared so that when the least significant bit of the search address is &ldquo;0&rdquo; and &ldquo;1&rdquo;, even and odd address banks respectively are used. The search object data is classified according to data belonging to the odd and even addresses in continuous addresses and allocated to these two storage units. Further, a search tree of the search address is constructed so that two data of object for a next search are stored in different storage units. Upon the binary search, addresses for the two storage units are set according to this search tree. Therefore, simultaneous readout of data is enabled, so that readout and comparison are carried out in parallel. Further, according to multiple division search of the invention, if 2 bits of the least significant bits of the search address are &ldquo;00&rdquo;, &ldquo;01&rdquo;, &ldquo;10&rdquo; and &ldquo;11&rdquo;, a search object data is stored in first through fourth banks respectively. A search tree of the search address is constructed so that four data of object for a next search are stored in different banks. Upon a search, an address for each bank is set according to the search tree so as to enable readout of data at the same time, thereby reducing time required for the search.

Binary data search method for selecting from among candidate data, and apparatus therefor

A method and apparatus for carrying out binary search based on a plurality of retrieval conditions. Retrieval object data is classified into higher order bits and lower order bits. A portion of retrieval key data, in correspondence with the higher order bits of the retrieval object data, constitutes first key data and a portion in correspondence with the lower order bits of the retrieval object data constitutes second retrieval key data. A higher order bit comparing circuit is provided for comparing the higher order bits of the retrieval object data with the first retrieval key data and a lower order bit comparing circuit and for comparing the lower order bits of the retrieval object data with the second retrieval key data. Further, there is provided a determining circuit for determining coincidence or non-coincidence between the retrieval key data and the retrieval object data in accordance with a comparison enabling bit EB indicating coincidence conditions, a comparison result of the higher order bit comparing circuit and comparison result of the lower bit comparing circuit

Method and apparatus for data retrieval

The invention relates to a network interface apparatus called a router or the like which is provided in a network system and relays the transmission of a data packet as a bundle of information. In order to know the permission or inhibition of communication of the data packet at a high speed while suppressing an increase in memory capacity, there is provided a coupling management table in which one VLAN ID is allocated to each terminal (each MAC address) and coupling information showing whether the communication from the terminal having a transmitting side VLAN ID to the terminal having a receiving side VLAN ID is permitted (logic &ldquo;1&rdquo;) or inhibited (logic &ldquo;0&rdquo;) has been stored at each of the coordinate points using the VLAN ID on the transmitting side and the VLAN ID on the receiving side as coordinates.

Network interface apparatus for transmitting a data packet

An associative memory device having a high speed and good performance is provided without degrading the simple design of a peripheral circuit of a conventional associative memory. The associative memory device has an N-bit first buffer and an M-bit second buffer in which W-bit data is stored through a data input port, detection device for detecting that the W-bit data is input to the first buffer k times or to the second buffer r times, a switch for alternately switching buffers in which the W-bit data is stored, and a search control for performing a search operation for a memory region by using data in the first or second buffer. By using data in the first or second buffer, during the search operation for the memory region of the associative memory, the W-bit data for the next search operation is input to the second or first buffer.

Associative memory device

There is provided a configurable electronic circuit board which comprises a board including many modular sockets in a minimum unit each having a size and the number of pins both standardized, the modular sockets being arranged regularly parallely and connected to each other at terminals thereof through simple wirings, a pin adapter composed of adapter pins insertable into the modular socket, of an adapter socket into which electronic circuit parts are insertable, and of socket wirings for making connection between the adapter socket and the adapter pins, a switching station adapter composed of adapter pins insertable into the modular socket, and of a wiring changeover switch and a fuse for determining the connection of wiring among the adapter pins, and a bypass adapter being inserted into a modular socket not used, and composed of adapter pins insertable into the modular socket, and of fixed wiring for simply bypass-connecting among the adapter pins, whereby an arbitrary circuit is realizable by inserting each adapter or electronic circuit part into an arbitrary modular socket. The configurable electronic circuit board is used to realize and verify a designed circuit.

Configurable electronic circuit board adapter therefor, and designing

There is provided a programmable one-board computer comprising a system board including wirings, one or more of microprocessor chips disposed at the center of said system board, and a plurality of programmable logic devices (PLD) disposed to surround said one or more of the microprocessor chips. Each said PLD may include a memory for defining an internal circuit thereof or may substitute partly thereof for an external memory device, or said PLDs may be comprised of large scale PLDs as inner PLDs thereof and small scale PLDs as outer PLDs thereof. The programmable one-board computer can realize an actual circuit altered from a newly designed logic circuit and laid out on the same. The actual circuit laid on the same can be used for verification.

Growing community of inventors

Chiba, Japan

Yoshihiro Ishida