Mitsubishi Denki Kabushiki Kaisha

Other

Mitsubishi Electric Semiconductor Software Corporation

Yoshihiro Inada

Shinji Yamashita

Miki Nishimoto

The AGC circuit is provided with an analog variable gain amplifying circuit which includes a plurality of fixed gain amplifiers and a selector for selecting one of the output signals of the plurality of fixed gain amplifiers, an A/D converter for receiving the selected output signal from the variable gain amplifying circuit, a digital band pass filter which allows only the burst signal and the color signal in the output signal from the A/D converter to pass through, and a digital AGC/detection circuit for controlling the gain of the variable gain amplifying circuit such that the burst signal remains stable and for amplifying the digital signal to obtain a digital output color signal such that the detected burst signal becomes equal in level to the digital reference signal. Thus, a more stable output signal can be obtained even with the variation in the ambient temperature or the power supply voltage.

Automatic gain control circuit

A demodulator circuit including: a signal generating circuit for generating a sine-wave signal and a cosine-wave signal whose frequencies are same as that of the carrier wave of a modulated signal, a multiplying circuit for multiplying the modulated signal by the sine-wave signal and the cosine-wave signal generated by the signal generating circuit, and a filtering circuit for eliminating the frequency twice as high as that of the carrier wave from each of the results of the computation conducted by the multiplying circuit. Due to this, no restriction is imposed by the frequency of the system clock signal in configuring the system as a whole.

Demodulator circuit which demodulates a signal without any restriction from a clock signal

There is disclosed a horizontal synchronizing signal generating circuit for generating a horizontal synchronizing signal which has no frequency variations and which is in phase with an entered composite synchronizing signal if the entered composite synchronizing signal is a nonstandard signal having a varying horizontal frequency. A horizontal counter circuit (5) counts a reference clock (V.sub.CL), and a window pulse generating circuit (4) outputs a window pulse signal (V.sub.W) which is low for a fixed time period when a counter output (V.sub.CT) equals a counter value (878) indicative of a standard output timing. A horizontal synchronizing signal separating circuit (1) outputs a horizontal synchronizing signal (V.sub.2) only when the composite synchronizing signal (V.sub.1) falls within the fixed time period. Then a horizontal phase judging circuit (2) outputs a standard signal flag (V.sub.3) and a synchronizing signal generating circuit (3) outputs the horizontal synchronizing signal (V.sub.2) in synchronism with the reference clock (V.sub.CL). When the composite synchronizing signal (V.sub.1) does not fall within the fixed time period, the horizontal phase judging circuit (2) outputs a nonstandard signal flag (V.sub.3), and the synchronizing signal generating circuit (3) outputs a horizontal synchronizing signal (V.sub.4) produced from the window pulse signal (V.sub.W).

Horizontal synchronizing signal generating circuit

A sampling circuit is not susceptible to an influence of structural components and environmental changes. A phase difference detecting circuit (5) detects a deviation of a sampling clock (.phi.2) from optimal sampling timing and outputs a phase difference signal. On the other hand, a phase reference signal (ORG) which is used as a reference to determine a phase advance and a phase lag is generated by a phase reference detecting circuit (4). In accordance with these signals, a sampling clock shifting circuit (2) shifts the sampling clock (.phi.2) so that the sampling clock (.phi.2) is activated at optimal sampling timing. Sampling is performed in accordance with such a sampling clock (.phi.2), whereby a basic signal is generated from which the phase reference signal (ORG) and the phase difference signal (i.e., an equivalent signal (EQU) and a non-equivalent signal (UPDN)) are generated. By means of feedback control, the sampling clock is automatically activated at optimal sampling timing.

Sampling circuit, phase reference detecting circuit and sampling clock

A composite synchronizing signal separation circuit in which separation of the composite synchronizing signal by a digital circuit is realized and such trouble as adjusting the time constant is not needed and a phase shift is reduced: a horizontal interruption receiving circuit 1 which is reset by a timing pulse signal at the time point of 3/4 from the starting time point of one horizontal synchronizing period, and separates and outputs a horizontal synchronizing signal HD from a composite synchronizing signal SYNC; a schedule counter circuit 2 which is reset by the horizontal synchronizing signal HD and outputs count value while counting up to a predetermined value in one horizontal synchronizing period; a timing decoding circuit 3 which decodes the count value and respectively outputs timing pulse signals at the time points of 1/4, 1/2 and 3/4 from the starting time point of one horizontal synchronizing period; and a vertical interruption receiving circuit 4 which samples the composite synchronizing signal SYNC by these signals and outputs a vertical synchronizing signal VD.

Growing community of inventors

Itami, Japan

Yoshihiro Inada